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2a152512a1
This patch adds support for CQ notifications through the standard verbs api. In order to achieve that, a new event queue (EQ) object is introduced, which is in charge of reporting completion events to the driver. On driver load, EQs are allocated and their affinity is set to a single cpu. When a user app creates a CQ with a completion channel, the completion vector number is converted to a EQ number, which is in charge of reporting the CQ events. In addition, the CQ creation admin command now returns an offset for the CQ doorbell, which is mapped to the userspace provider and is used to arm the CQ when requested by the user. The EQs use a single doorbell (located on the registers BAR), which encodes the EQ number and arm as part of the doorbell value. The EQs are polled by the driver on each new EQE, and arm it when the poll is completed. Link: https://lore.kernel.org/r/20211003105605.29222-1-galpress@amazon.com Reviewed-by: Firas JahJah <firasj@amazon.com> Reviewed-by: Yossi Leybovich <sleybo@amazon.com> Signed-off-by: Gal Pressman <galpress@amazon.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
101 lines
4.5 KiB
C
101 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
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/*
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* Copyright 2018-2021 Amazon.com, Inc. or its affiliates. All rights reserved.
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*/
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#ifndef _EFA_REGS_H_
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#define _EFA_REGS_H_
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enum efa_regs_reset_reason_types {
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EFA_REGS_RESET_NORMAL = 0,
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/* Keep alive timeout */
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EFA_REGS_RESET_KEEP_ALIVE_TO = 1,
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EFA_REGS_RESET_ADMIN_TO = 2,
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EFA_REGS_RESET_INIT_ERR = 3,
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EFA_REGS_RESET_DRIVER_INVALID_STATE = 4,
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EFA_REGS_RESET_OS_TRIGGER = 5,
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EFA_REGS_RESET_SHUTDOWN = 6,
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EFA_REGS_RESET_USER_TRIGGER = 7,
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EFA_REGS_RESET_GENERIC = 8,
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};
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/* efa_registers offsets */
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/* 0 base */
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#define EFA_REGS_VERSION_OFF 0x0
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#define EFA_REGS_CONTROLLER_VERSION_OFF 0x4
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#define EFA_REGS_CAPS_OFF 0x8
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#define EFA_REGS_AQ_BASE_LO_OFF 0x10
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#define EFA_REGS_AQ_BASE_HI_OFF 0x14
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#define EFA_REGS_AQ_CAPS_OFF 0x18
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#define EFA_REGS_ACQ_BASE_LO_OFF 0x20
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#define EFA_REGS_ACQ_BASE_HI_OFF 0x24
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#define EFA_REGS_ACQ_CAPS_OFF 0x28
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#define EFA_REGS_AQ_PROD_DB_OFF 0x2c
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#define EFA_REGS_AENQ_CAPS_OFF 0x34
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#define EFA_REGS_AENQ_BASE_LO_OFF 0x38
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#define EFA_REGS_AENQ_BASE_HI_OFF 0x3c
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#define EFA_REGS_AENQ_CONS_DB_OFF 0x40
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#define EFA_REGS_INTR_MASK_OFF 0x4c
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#define EFA_REGS_DEV_CTL_OFF 0x54
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#define EFA_REGS_DEV_STS_OFF 0x58
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#define EFA_REGS_MMIO_REG_READ_OFF 0x5c
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#define EFA_REGS_MMIO_RESP_LO_OFF 0x60
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#define EFA_REGS_MMIO_RESP_HI_OFF 0x64
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#define EFA_REGS_EQ_DB_OFF 0x68
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/* version register */
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#define EFA_REGS_VERSION_MINOR_VERSION_MASK 0xff
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#define EFA_REGS_VERSION_MAJOR_VERSION_MASK 0xff00
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/* controller_version register */
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#define EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK 0xff
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#define EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK 0xff00
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#define EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK 0xff0000
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#define EFA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK 0xff000000
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/* caps register */
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#define EFA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x1
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#define EFA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e
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#define EFA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff00
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#define EFA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf0000
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/* aq_caps register */
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#define EFA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff
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#define EFA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK 0xffff0000
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/* acq_caps register */
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#define EFA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK 0xffff
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#define EFA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK 0xff0000
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#define EFA_REGS_ACQ_CAPS_ACQ_MSIX_VECTOR_MASK 0xff000000
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/* aenq_caps register */
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#define EFA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK 0xffff
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#define EFA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK 0xff0000
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#define EFA_REGS_AENQ_CAPS_AENQ_MSIX_VECTOR_MASK 0xff000000
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/* intr_mask register */
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#define EFA_REGS_INTR_MASK_EN_MASK 0x1
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/* dev_ctl register */
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#define EFA_REGS_DEV_CTL_DEV_RESET_MASK 0x1
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#define EFA_REGS_DEV_CTL_AQ_RESTART_MASK 0x2
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#define EFA_REGS_DEV_CTL_RESET_REASON_MASK 0xf0000000
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/* dev_sts register */
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#define EFA_REGS_DEV_STS_READY_MASK 0x1
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#define EFA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2
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#define EFA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4
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#define EFA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK 0x8
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#define EFA_REGS_DEV_STS_RESET_FINISHED_MASK 0x10
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#define EFA_REGS_DEV_STS_FATAL_ERROR_MASK 0x20
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/* mmio_reg_read register */
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#define EFA_REGS_MMIO_REG_READ_REQ_ID_MASK 0xffff
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#define EFA_REGS_MMIO_REG_READ_REG_OFF_MASK 0xffff0000
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/* eq_db register */
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#define EFA_REGS_EQ_DB_EQN_MASK 0xffff
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#define EFA_REGS_EQ_DB_ARM_MASK 0x80000000
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#endif /* _EFA_REGS_H_ */
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