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![Cai Huoqing](/assets/img/avatar_default.png)
use SPDX-License-Identifier instead of a verbose license text Link: https://lore.kernel.org/r/20210823042622.109-1-caihuoqing@baidu.com Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
816 lines
21 KiB
C
816 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
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/*
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* Copyright(c) 2015, 2016 Intel Corporation.
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*/
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/vmalloc.h>
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#include "hfi.h"
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/* for the given bus number, return the CSR for reading an i2c line */
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static inline u32 i2c_in_csr(u32 bus_num)
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{
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return bus_num ? ASIC_QSFP2_IN : ASIC_QSFP1_IN;
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}
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/* for the given bus number, return the CSR for writing an i2c line */
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static inline u32 i2c_oe_csr(u32 bus_num)
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{
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return bus_num ? ASIC_QSFP2_OE : ASIC_QSFP1_OE;
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}
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static void hfi1_setsda(void *data, int state)
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{
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struct hfi1_i2c_bus *bus = (struct hfi1_i2c_bus *)data;
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struct hfi1_devdata *dd = bus->controlling_dd;
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u64 reg;
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u32 target_oe;
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target_oe = i2c_oe_csr(bus->num);
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reg = read_csr(dd, target_oe);
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/*
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* The OE bit value is inverted and connected to the pin. When
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* OE is 0 the pin is left to be pulled up, when the OE is 1
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* the pin is driven low. This matches the "open drain" or "open
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* collector" convention.
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*/
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if (state)
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reg &= ~QSFP_HFI0_I2CDAT;
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else
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reg |= QSFP_HFI0_I2CDAT;
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write_csr(dd, target_oe, reg);
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/* do a read to force the write into the chip */
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(void)read_csr(dd, target_oe);
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}
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static void hfi1_setscl(void *data, int state)
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{
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struct hfi1_i2c_bus *bus = (struct hfi1_i2c_bus *)data;
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struct hfi1_devdata *dd = bus->controlling_dd;
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u64 reg;
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u32 target_oe;
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target_oe = i2c_oe_csr(bus->num);
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reg = read_csr(dd, target_oe);
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/*
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* The OE bit value is inverted and connected to the pin. When
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* OE is 0 the pin is left to be pulled up, when the OE is 1
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* the pin is driven low. This matches the "open drain" or "open
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* collector" convention.
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*/
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if (state)
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reg &= ~QSFP_HFI0_I2CCLK;
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else
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reg |= QSFP_HFI0_I2CCLK;
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write_csr(dd, target_oe, reg);
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/* do a read to force the write into the chip */
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(void)read_csr(dd, target_oe);
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}
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static int hfi1_getsda(void *data)
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{
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struct hfi1_i2c_bus *bus = (struct hfi1_i2c_bus *)data;
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u64 reg;
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u32 target_in;
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hfi1_setsda(data, 1); /* clear OE so we do not pull line down */
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udelay(2); /* 1us pull up + 250ns hold */
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target_in = i2c_in_csr(bus->num);
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reg = read_csr(bus->controlling_dd, target_in);
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return !!(reg & QSFP_HFI0_I2CDAT);
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}
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static int hfi1_getscl(void *data)
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{
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struct hfi1_i2c_bus *bus = (struct hfi1_i2c_bus *)data;
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u64 reg;
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u32 target_in;
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hfi1_setscl(data, 1); /* clear OE so we do not pull line down */
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udelay(2); /* 1us pull up + 250ns hold */
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target_in = i2c_in_csr(bus->num);
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reg = read_csr(bus->controlling_dd, target_in);
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return !!(reg & QSFP_HFI0_I2CCLK);
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}
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/*
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* Allocate and initialize the given i2c bus number.
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* Returns NULL on failure.
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*/
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static struct hfi1_i2c_bus *init_i2c_bus(struct hfi1_devdata *dd,
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struct hfi1_asic_data *ad, int num)
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{
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struct hfi1_i2c_bus *bus;
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int ret;
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bus = kzalloc(sizeof(*bus), GFP_KERNEL);
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if (!bus)
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return NULL;
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bus->controlling_dd = dd;
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bus->num = num; /* our bus number */
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bus->algo.setsda = hfi1_setsda;
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bus->algo.setscl = hfi1_setscl;
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bus->algo.getsda = hfi1_getsda;
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bus->algo.getscl = hfi1_getscl;
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bus->algo.udelay = 5;
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bus->algo.timeout = usecs_to_jiffies(100000);
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bus->algo.data = bus;
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bus->adapter.owner = THIS_MODULE;
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bus->adapter.algo_data = &bus->algo;
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bus->adapter.dev.parent = &dd->pcidev->dev;
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snprintf(bus->adapter.name, sizeof(bus->adapter.name),
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"hfi1_i2c%d", num);
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ret = i2c_bit_add_bus(&bus->adapter);
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if (ret) {
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dd_dev_info(dd, "%s: unable to add i2c bus %d, err %d\n",
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__func__, num, ret);
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kfree(bus);
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return NULL;
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}
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return bus;
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}
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/*
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* Initialize i2c buses.
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* Return 0 on success, -errno on error.
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*/
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int set_up_i2c(struct hfi1_devdata *dd, struct hfi1_asic_data *ad)
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{
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ad->i2c_bus0 = init_i2c_bus(dd, ad, 0);
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ad->i2c_bus1 = init_i2c_bus(dd, ad, 1);
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if (!ad->i2c_bus0 || !ad->i2c_bus1)
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return -ENOMEM;
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return 0;
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};
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static void clean_i2c_bus(struct hfi1_i2c_bus *bus)
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{
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if (bus) {
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i2c_del_adapter(&bus->adapter);
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kfree(bus);
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}
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}
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void clean_up_i2c(struct hfi1_devdata *dd, struct hfi1_asic_data *ad)
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{
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if (!ad)
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return;
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clean_i2c_bus(ad->i2c_bus0);
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ad->i2c_bus0 = NULL;
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clean_i2c_bus(ad->i2c_bus1);
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ad->i2c_bus1 = NULL;
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}
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static int i2c_bus_write(struct hfi1_devdata *dd, struct hfi1_i2c_bus *i2c,
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u8 slave_addr, int offset, int offset_size,
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u8 *data, u16 len)
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{
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int ret;
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int num_msgs;
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u8 offset_bytes[2];
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struct i2c_msg msgs[2];
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switch (offset_size) {
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case 0:
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num_msgs = 1;
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msgs[0].addr = slave_addr;
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msgs[0].flags = 0;
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msgs[0].len = len;
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msgs[0].buf = data;
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break;
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case 2:
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offset_bytes[1] = (offset >> 8) & 0xff;
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fallthrough;
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case 1:
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num_msgs = 2;
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offset_bytes[0] = offset & 0xff;
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msgs[0].addr = slave_addr;
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msgs[0].flags = 0;
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msgs[0].len = offset_size;
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msgs[0].buf = offset_bytes;
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msgs[1].addr = slave_addr;
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msgs[1].flags = I2C_M_NOSTART;
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msgs[1].len = len;
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msgs[1].buf = data;
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break;
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default:
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return -EINVAL;
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}
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i2c->controlling_dd = dd;
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ret = i2c_transfer(&i2c->adapter, msgs, num_msgs);
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if (ret != num_msgs) {
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dd_dev_err(dd, "%s: bus %d, i2c slave 0x%x, offset 0x%x, len 0x%x; write failed, ret %d\n",
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__func__, i2c->num, slave_addr, offset, len, ret);
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return ret < 0 ? ret : -EIO;
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}
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return 0;
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}
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static int i2c_bus_read(struct hfi1_devdata *dd, struct hfi1_i2c_bus *bus,
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u8 slave_addr, int offset, int offset_size,
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u8 *data, u16 len)
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{
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int ret;
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int num_msgs;
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u8 offset_bytes[2];
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struct i2c_msg msgs[2];
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switch (offset_size) {
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case 0:
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num_msgs = 1;
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msgs[0].addr = slave_addr;
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msgs[0].flags = I2C_M_RD;
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msgs[0].len = len;
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msgs[0].buf = data;
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break;
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case 2:
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offset_bytes[1] = (offset >> 8) & 0xff;
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fallthrough;
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case 1:
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num_msgs = 2;
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offset_bytes[0] = offset & 0xff;
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msgs[0].addr = slave_addr;
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msgs[0].flags = 0;
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msgs[0].len = offset_size;
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msgs[0].buf = offset_bytes;
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msgs[1].addr = slave_addr;
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msgs[1].flags = I2C_M_RD;
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msgs[1].len = len;
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msgs[1].buf = data;
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break;
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default:
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return -EINVAL;
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}
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bus->controlling_dd = dd;
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ret = i2c_transfer(&bus->adapter, msgs, num_msgs);
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if (ret != num_msgs) {
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dd_dev_err(dd, "%s: bus %d, i2c slave 0x%x, offset 0x%x, len 0x%x; read failed, ret %d\n",
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__func__, bus->num, slave_addr, offset, len, ret);
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return ret < 0 ? ret : -EIO;
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}
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return 0;
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}
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/*
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* Raw i2c write. No set-up or lock checking.
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*
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* Return 0 on success, -errno on error.
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*/
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static int __i2c_write(struct hfi1_pportdata *ppd, u32 target, int i2c_addr,
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int offset, void *bp, int len)
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{
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struct hfi1_devdata *dd = ppd->dd;
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struct hfi1_i2c_bus *bus;
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u8 slave_addr;
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int offset_size;
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bus = target ? dd->asic_data->i2c_bus1 : dd->asic_data->i2c_bus0;
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slave_addr = (i2c_addr & 0xff) >> 1; /* convert to 7-bit addr */
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offset_size = (i2c_addr >> 8) & 0x3;
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return i2c_bus_write(dd, bus, slave_addr, offset, offset_size, bp, len);
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}
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/*
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* Caller must hold the i2c chain resource.
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*
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* Return number of bytes written, or -errno.
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*/
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int i2c_write(struct hfi1_pportdata *ppd, u32 target, int i2c_addr, int offset,
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void *bp, int len)
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{
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int ret;
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if (!check_chip_resource(ppd->dd, i2c_target(target), __func__))
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return -EACCES;
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ret = __i2c_write(ppd, target, i2c_addr, offset, bp, len);
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if (ret)
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return ret;
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return len;
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}
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/*
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* Raw i2c read. No set-up or lock checking.
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*
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* Return 0 on success, -errno on error.
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*/
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static int __i2c_read(struct hfi1_pportdata *ppd, u32 target, int i2c_addr,
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int offset, void *bp, int len)
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{
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struct hfi1_devdata *dd = ppd->dd;
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struct hfi1_i2c_bus *bus;
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u8 slave_addr;
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int offset_size;
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bus = target ? dd->asic_data->i2c_bus1 : dd->asic_data->i2c_bus0;
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slave_addr = (i2c_addr & 0xff) >> 1; /* convert to 7-bit addr */
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offset_size = (i2c_addr >> 8) & 0x3;
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return i2c_bus_read(dd, bus, slave_addr, offset, offset_size, bp, len);
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}
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/*
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* Caller must hold the i2c chain resource.
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*
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* Return number of bytes read, or -errno.
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*/
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int i2c_read(struct hfi1_pportdata *ppd, u32 target, int i2c_addr, int offset,
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void *bp, int len)
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{
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int ret;
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if (!check_chip_resource(ppd->dd, i2c_target(target), __func__))
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return -EACCES;
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ret = __i2c_read(ppd, target, i2c_addr, offset, bp, len);
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if (ret)
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return ret;
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return len;
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}
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/*
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* Write page n, offset m of QSFP memory as defined by SFF 8636
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* by writing @addr = ((256 * n) + m)
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*
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* Caller must hold the i2c chain resource.
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*
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* Return number of bytes written or -errno.
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*/
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int qsfp_write(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
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int len)
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{
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int count = 0;
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int offset;
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int nwrite;
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int ret = 0;
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u8 page;
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if (!check_chip_resource(ppd->dd, i2c_target(target), __func__))
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return -EACCES;
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while (count < len) {
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/*
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* Set the qsfp page based on a zero-based address
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* and a page size of QSFP_PAGESIZE bytes.
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*/
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page = (u8)(addr / QSFP_PAGESIZE);
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ret = __i2c_write(ppd, target, QSFP_DEV | QSFP_OFFSET_SIZE,
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QSFP_PAGE_SELECT_BYTE_OFFS, &page, 1);
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/* QSFPs require a 5-10msec delay after write operations */
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mdelay(5);
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if (ret) {
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hfi1_dev_porterr(ppd->dd, ppd->port,
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"QSFP chain %d can't write QSFP_PAGE_SELECT_BYTE: %d\n",
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target, ret);
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break;
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}
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offset = addr % QSFP_PAGESIZE;
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nwrite = len - count;
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/* truncate write to boundary if crossing boundary */
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if (((addr % QSFP_RW_BOUNDARY) + nwrite) > QSFP_RW_BOUNDARY)
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nwrite = QSFP_RW_BOUNDARY - (addr % QSFP_RW_BOUNDARY);
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ret = __i2c_write(ppd, target, QSFP_DEV | QSFP_OFFSET_SIZE,
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offset, bp + count, nwrite);
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/* QSFPs require a 5-10msec delay after write operations */
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mdelay(5);
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if (ret) /* stop on error */
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break;
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count += nwrite;
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addr += nwrite;
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}
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if (ret < 0)
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return ret;
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return count;
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}
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/*
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* Perform a stand-alone single QSFP write. Acquire the resource, do the
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* write, then release the resource.
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*/
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int one_qsfp_write(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
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int len)
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{
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struct hfi1_devdata *dd = ppd->dd;
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u32 resource = qsfp_resource(dd);
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int ret;
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ret = acquire_chip_resource(dd, resource, QSFP_WAIT);
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if (ret)
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return ret;
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ret = qsfp_write(ppd, target, addr, bp, len);
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release_chip_resource(dd, resource);
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return ret;
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}
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/*
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* Access page n, offset m of QSFP memory as defined by SFF 8636
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* by reading @addr = ((256 * n) + m)
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*
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* Caller must hold the i2c chain resource.
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*
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* Return the number of bytes read or -errno.
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*/
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int qsfp_read(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
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int len)
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{
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int count = 0;
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int offset;
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int nread;
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int ret = 0;
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u8 page;
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if (!check_chip_resource(ppd->dd, i2c_target(target), __func__))
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return -EACCES;
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while (count < len) {
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/*
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* Set the qsfp page based on a zero-based address
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* and a page size of QSFP_PAGESIZE bytes.
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*/
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page = (u8)(addr / QSFP_PAGESIZE);
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ret = __i2c_write(ppd, target, QSFP_DEV | QSFP_OFFSET_SIZE,
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QSFP_PAGE_SELECT_BYTE_OFFS, &page, 1);
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/* QSFPs require a 5-10msec delay after write operations */
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mdelay(5);
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if (ret) {
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hfi1_dev_porterr(ppd->dd, ppd->port,
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"QSFP chain %d can't write QSFP_PAGE_SELECT_BYTE: %d\n",
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target, ret);
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break;
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}
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offset = addr % QSFP_PAGESIZE;
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nread = len - count;
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/* truncate read to boundary if crossing boundary */
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if (((addr % QSFP_RW_BOUNDARY) + nread) > QSFP_RW_BOUNDARY)
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nread = QSFP_RW_BOUNDARY - (addr % QSFP_RW_BOUNDARY);
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ret = __i2c_read(ppd, target, QSFP_DEV | QSFP_OFFSET_SIZE,
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offset, bp + count, nread);
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if (ret) /* stop on error */
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break;
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count += nread;
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addr += nread;
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}
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if (ret < 0)
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return ret;
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return count;
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}
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/*
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|
* Perform a stand-alone single QSFP read. Acquire the resource, do the
|
|
* read, then release the resource.
|
|
*/
|
|
int one_qsfp_read(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
|
|
int len)
|
|
{
|
|
struct hfi1_devdata *dd = ppd->dd;
|
|
u32 resource = qsfp_resource(dd);
|
|
int ret;
|
|
|
|
ret = acquire_chip_resource(dd, resource, QSFP_WAIT);
|
|
if (ret)
|
|
return ret;
|
|
ret = qsfp_read(ppd, target, addr, bp, len);
|
|
release_chip_resource(dd, resource);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* This function caches the QSFP memory range in 128 byte chunks.
|
|
* As an example, the next byte after address 255 is byte 128 from
|
|
* upper page 01H (if existing) rather than byte 0 from lower page 00H.
|
|
* Access page n, offset m of QSFP memory as defined by SFF 8636
|
|
* in the cache by reading byte ((128 * n) + m)
|
|
* The calls to qsfp_{read,write} in this function correctly handle the
|
|
* address map difference between this mapping and the mapping implemented
|
|
* by those functions
|
|
*
|
|
* The caller must be holding the QSFP i2c chain resource.
|
|
*/
|
|
int refresh_qsfp_cache(struct hfi1_pportdata *ppd, struct qsfp_data *cp)
|
|
{
|
|
u32 target = ppd->dd->hfi1_id;
|
|
int ret;
|
|
unsigned long flags;
|
|
u8 *cache = &cp->cache[0];
|
|
|
|
/* ensure sane contents on invalid reads, for cable swaps */
|
|
memset(cache, 0, (QSFP_MAX_NUM_PAGES * 128));
|
|
spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
|
|
ppd->qsfp_info.cache_valid = 0;
|
|
spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags);
|
|
|
|
if (!qsfp_mod_present(ppd)) {
|
|
ret = -ENODEV;
|
|
goto bail;
|
|
}
|
|
|
|
ret = qsfp_read(ppd, target, 0, cache, QSFP_PAGESIZE);
|
|
if (ret != QSFP_PAGESIZE) {
|
|
dd_dev_info(ppd->dd,
|
|
"%s: Page 0 read failed, expected %d, got %d\n",
|
|
__func__, QSFP_PAGESIZE, ret);
|
|
goto bail;
|
|
}
|
|
|
|
/* Is paging enabled? */
|
|
if (!(cache[2] & 4)) {
|
|
/* Paging enabled, page 03 required */
|
|
if ((cache[195] & 0xC0) == 0xC0) {
|
|
/* all */
|
|
ret = qsfp_read(ppd, target, 384, cache + 256, 128);
|
|
if (ret <= 0 || ret != 128) {
|
|
dd_dev_info(ppd->dd, "%s failed\n", __func__);
|
|
goto bail;
|
|
}
|
|
ret = qsfp_read(ppd, target, 640, cache + 384, 128);
|
|
if (ret <= 0 || ret != 128) {
|
|
dd_dev_info(ppd->dd, "%s failed\n", __func__);
|
|
goto bail;
|
|
}
|
|
ret = qsfp_read(ppd, target, 896, cache + 512, 128);
|
|
if (ret <= 0 || ret != 128) {
|
|
dd_dev_info(ppd->dd, "%s failed\n", __func__);
|
|
goto bail;
|
|
}
|
|
} else if ((cache[195] & 0x80) == 0x80) {
|
|
/* only page 2 and 3 */
|
|
ret = qsfp_read(ppd, target, 640, cache + 384, 128);
|
|
if (ret <= 0 || ret != 128) {
|
|
dd_dev_info(ppd->dd, "%s failed\n", __func__);
|
|
goto bail;
|
|
}
|
|
ret = qsfp_read(ppd, target, 896, cache + 512, 128);
|
|
if (ret <= 0 || ret != 128) {
|
|
dd_dev_info(ppd->dd, "%s failed\n", __func__);
|
|
goto bail;
|
|
}
|
|
} else if ((cache[195] & 0x40) == 0x40) {
|
|
/* only page 1 and 3 */
|
|
ret = qsfp_read(ppd, target, 384, cache + 256, 128);
|
|
if (ret <= 0 || ret != 128) {
|
|
dd_dev_info(ppd->dd, "%s failed\n", __func__);
|
|
goto bail;
|
|
}
|
|
ret = qsfp_read(ppd, target, 896, cache + 512, 128);
|
|
if (ret <= 0 || ret != 128) {
|
|
dd_dev_info(ppd->dd, "%s failed\n", __func__);
|
|
goto bail;
|
|
}
|
|
} else {
|
|
/* only page 3 */
|
|
ret = qsfp_read(ppd, target, 896, cache + 512, 128);
|
|
if (ret <= 0 || ret != 128) {
|
|
dd_dev_info(ppd->dd, "%s failed\n", __func__);
|
|
goto bail;
|
|
}
|
|
}
|
|
}
|
|
|
|
spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
|
|
ppd->qsfp_info.cache_valid = 1;
|
|
ppd->qsfp_info.cache_refresh_required = 0;
|
|
spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags);
|
|
|
|
return 0;
|
|
|
|
bail:
|
|
memset(cache, 0, (QSFP_MAX_NUM_PAGES * 128));
|
|
return ret;
|
|
}
|
|
|
|
const char * const hfi1_qsfp_devtech[16] = {
|
|
"850nm VCSEL", "1310nm VCSEL", "1550nm VCSEL", "1310nm FP",
|
|
"1310nm DFB", "1550nm DFB", "1310nm EML", "1550nm EML",
|
|
"Cu Misc", "1490nm DFB", "Cu NoEq", "Cu Eq",
|
|
"Undef", "Cu Active BothEq", "Cu FarEq", "Cu NearEq"
|
|
};
|
|
|
|
#define QSFP_DUMP_CHUNK 16 /* Holds longest string */
|
|
#define QSFP_DEFAULT_HDR_CNT 224
|
|
|
|
#define QSFP_PWR(pbyte) (((pbyte) >> 6) & 3)
|
|
#define QSFP_HIGH_PWR(pbyte) ((pbyte) & 3)
|
|
/* For use with QSFP_HIGH_PWR macro */
|
|
#define QSFP_HIGH_PWR_UNUSED 0 /* Bits [1:0] = 00 implies low power module */
|
|
|
|
/*
|
|
* Takes power class byte [Page 00 Byte 129] in SFF 8636
|
|
* Returns power class as integer (1 through 7, per SFF 8636 rev 2.4)
|
|
*/
|
|
int get_qsfp_power_class(u8 power_byte)
|
|
{
|
|
if (QSFP_HIGH_PWR(power_byte) == QSFP_HIGH_PWR_UNUSED)
|
|
/* power classes count from 1, their bit encodings from 0 */
|
|
return (QSFP_PWR(power_byte) + 1);
|
|
/*
|
|
* 00 in the high power classes stands for unused, bringing
|
|
* balance to the off-by-1 offset above, we add 4 here to
|
|
* account for the difference between the low and high power
|
|
* groups
|
|
*/
|
|
return (QSFP_HIGH_PWR(power_byte) + 4);
|
|
}
|
|
|
|
int qsfp_mod_present(struct hfi1_pportdata *ppd)
|
|
{
|
|
struct hfi1_devdata *dd = ppd->dd;
|
|
u64 reg;
|
|
|
|
reg = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_IN : ASIC_QSFP1_IN);
|
|
return !(reg & QSFP_HFI0_MODPRST_N);
|
|
}
|
|
|
|
/*
|
|
* This function maps QSFP memory addresses in 128 byte chunks in the following
|
|
* fashion per the CableInfo SMA query definition in the IBA 1.3 spec/OPA Gen 1
|
|
* spec
|
|
* For addr 000-127, lower page 00h
|
|
* For addr 128-255, upper page 00h
|
|
* For addr 256-383, upper page 01h
|
|
* For addr 384-511, upper page 02h
|
|
* For addr 512-639, upper page 03h
|
|
*
|
|
* For addresses beyond this range, it returns the invalid range of data buffer
|
|
* set to 0.
|
|
* For upper pages that are optional, if they are not valid, returns the
|
|
* particular range of bytes in the data buffer set to 0.
|
|
*/
|
|
int get_cable_info(struct hfi1_devdata *dd, u32 port_num, u32 addr, u32 len,
|
|
u8 *data)
|
|
{
|
|
struct hfi1_pportdata *ppd;
|
|
u32 excess_len = len;
|
|
int ret = 0, offset = 0;
|
|
|
|
if (port_num > dd->num_pports || port_num < 1) {
|
|
dd_dev_info(dd, "%s: Invalid port number %d\n",
|
|
__func__, port_num);
|
|
ret = -EINVAL;
|
|
goto set_zeroes;
|
|
}
|
|
|
|
ppd = dd->pport + (port_num - 1);
|
|
if (!qsfp_mod_present(ppd)) {
|
|
ret = -ENODEV;
|
|
goto set_zeroes;
|
|
}
|
|
|
|
if (!ppd->qsfp_info.cache_valid) {
|
|
ret = -EINVAL;
|
|
goto set_zeroes;
|
|
}
|
|
|
|
if (addr >= (QSFP_MAX_NUM_PAGES * 128)) {
|
|
ret = -ERANGE;
|
|
goto set_zeroes;
|
|
}
|
|
|
|
if ((addr + len) > (QSFP_MAX_NUM_PAGES * 128)) {
|
|
excess_len = (addr + len) - (QSFP_MAX_NUM_PAGES * 128);
|
|
memcpy(data, &ppd->qsfp_info.cache[addr], (len - excess_len));
|
|
data += (len - excess_len);
|
|
goto set_zeroes;
|
|
}
|
|
|
|
memcpy(data, &ppd->qsfp_info.cache[addr], len);
|
|
|
|
if (addr <= QSFP_MONITOR_VAL_END &&
|
|
(addr + len) >= QSFP_MONITOR_VAL_START) {
|
|
/* Overlap with the dynamic channel monitor range */
|
|
if (addr < QSFP_MONITOR_VAL_START) {
|
|
if (addr + len <= QSFP_MONITOR_VAL_END)
|
|
len = addr + len - QSFP_MONITOR_VAL_START;
|
|
else
|
|
len = QSFP_MONITOR_RANGE;
|
|
offset = QSFP_MONITOR_VAL_START - addr;
|
|
addr = QSFP_MONITOR_VAL_START;
|
|
} else if (addr == QSFP_MONITOR_VAL_START) {
|
|
offset = 0;
|
|
if (addr + len > QSFP_MONITOR_VAL_END)
|
|
len = QSFP_MONITOR_RANGE;
|
|
} else {
|
|
offset = 0;
|
|
if (addr + len > QSFP_MONITOR_VAL_END)
|
|
len = QSFP_MONITOR_VAL_END - addr + 1;
|
|
}
|
|
/* Refresh the values of the dynamic monitors from the cable */
|
|
ret = one_qsfp_read(ppd, dd->hfi1_id, addr, data + offset, len);
|
|
if (ret != len) {
|
|
ret = -EAGAIN;
|
|
goto set_zeroes;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
set_zeroes:
|
|
memset(data, 0, excess_len);
|
|
return ret;
|
|
}
|
|
|
|
static const char *pwr_codes[8] = {"N/AW",
|
|
"1.5W",
|
|
"2.0W",
|
|
"2.5W",
|
|
"3.5W",
|
|
"4.0W",
|
|
"4.5W",
|
|
"5.0W"
|
|
};
|
|
|
|
int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len)
|
|
{
|
|
u8 *cache = &ppd->qsfp_info.cache[0];
|
|
u8 bin_buff[QSFP_DUMP_CHUNK];
|
|
char lenstr[6];
|
|
int sofar;
|
|
int bidx = 0;
|
|
u8 *atten = &cache[QSFP_ATTEN_OFFS];
|
|
u8 *vendor_oui = &cache[QSFP_VOUI_OFFS];
|
|
u8 power_byte = 0;
|
|
|
|
sofar = 0;
|
|
lenstr[0] = ' ';
|
|
lenstr[1] = '\0';
|
|
|
|
if (ppd->qsfp_info.cache_valid) {
|
|
if (QSFP_IS_CU(cache[QSFP_MOD_TECH_OFFS]))
|
|
snprintf(lenstr, sizeof(lenstr), "%dM ",
|
|
cache[QSFP_MOD_LEN_OFFS]);
|
|
|
|
power_byte = cache[QSFP_MOD_PWR_OFFS];
|
|
sofar += scnprintf(buf + sofar, len - sofar, "PWR:%.3sW\n",
|
|
pwr_codes[get_qsfp_power_class(power_byte)]);
|
|
|
|
sofar += scnprintf(buf + sofar, len - sofar, "TECH:%s%s\n",
|
|
lenstr,
|
|
hfi1_qsfp_devtech[(cache[QSFP_MOD_TECH_OFFS]) >> 4]);
|
|
|
|
sofar += scnprintf(buf + sofar, len - sofar, "Vendor:%.*s\n",
|
|
QSFP_VEND_LEN, &cache[QSFP_VEND_OFFS]);
|
|
|
|
sofar += scnprintf(buf + sofar, len - sofar, "OUI:%06X\n",
|
|
QSFP_OUI(vendor_oui));
|
|
|
|
sofar += scnprintf(buf + sofar, len - sofar, "Part#:%.*s\n",
|
|
QSFP_PN_LEN, &cache[QSFP_PN_OFFS]);
|
|
|
|
sofar += scnprintf(buf + sofar, len - sofar, "Rev:%.*s\n",
|
|
QSFP_REV_LEN, &cache[QSFP_REV_OFFS]);
|
|
|
|
if (QSFP_IS_CU(cache[QSFP_MOD_TECH_OFFS]))
|
|
sofar += scnprintf(buf + sofar, len - sofar,
|
|
"Atten:%d, %d\n",
|
|
QSFP_ATTEN_SDR(atten),
|
|
QSFP_ATTEN_DDR(atten));
|
|
|
|
sofar += scnprintf(buf + sofar, len - sofar, "Serial:%.*s\n",
|
|
QSFP_SN_LEN, &cache[QSFP_SN_OFFS]);
|
|
|
|
sofar += scnprintf(buf + sofar, len - sofar, "Date:%.*s\n",
|
|
QSFP_DATE_LEN, &cache[QSFP_DATE_OFFS]);
|
|
|
|
sofar += scnprintf(buf + sofar, len - sofar, "Lot:%.*s\n",
|
|
QSFP_LOT_LEN, &cache[QSFP_LOT_OFFS]);
|
|
|
|
while (bidx < QSFP_DEFAULT_HDR_CNT) {
|
|
int iidx;
|
|
|
|
memcpy(bin_buff, &cache[bidx], QSFP_DUMP_CHUNK);
|
|
for (iidx = 0; iidx < QSFP_DUMP_CHUNK; ++iidx) {
|
|
sofar += scnprintf(buf + sofar, len - sofar,
|
|
" %02X", bin_buff[iidx]);
|
|
}
|
|
sofar += scnprintf(buf + sofar, len - sofar, "\n");
|
|
bidx += QSFP_DUMP_CHUNK;
|
|
}
|
|
}
|
|
return sofar;
|
|
}
|