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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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![Cai Huoqing](/assets/img/avatar_default.png)
use SPDX-License-Identifier instead of a verbose license text Link: https://lore.kernel.org/r/20210823042622.109-1-caihuoqing@baidu.com Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
1034 lines
30 KiB
C
1034 lines
30 KiB
C
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
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/*
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* Copyright(c) 2015 - 2018 Intel Corporation.
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*/
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#ifndef _HFI1_SDMA_H
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#define _HFI1_SDMA_H
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#include <linux/types.h>
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#include <linux/list.h>
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#include <asm/byteorder.h>
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#include <linux/workqueue.h>
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#include <linux/rculist.h>
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#include "hfi.h"
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#include "verbs.h"
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#include "sdma_txreq.h"
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/* Hardware limit */
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#define MAX_DESC 64
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/* Hardware limit for SDMA packet size */
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#define MAX_SDMA_PKT_SIZE ((16 * 1024) - 1)
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#define SDMA_MAP_NONE 0
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#define SDMA_MAP_SINGLE 1
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#define SDMA_MAP_PAGE 2
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#define SDMA_AHG_VALUE_MASK 0xffff
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#define SDMA_AHG_VALUE_SHIFT 0
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#define SDMA_AHG_INDEX_MASK 0xf
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#define SDMA_AHG_INDEX_SHIFT 16
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#define SDMA_AHG_FIELD_LEN_MASK 0xf
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#define SDMA_AHG_FIELD_LEN_SHIFT 20
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#define SDMA_AHG_FIELD_START_MASK 0x1f
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#define SDMA_AHG_FIELD_START_SHIFT 24
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#define SDMA_AHG_UPDATE_ENABLE_MASK 0x1
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#define SDMA_AHG_UPDATE_ENABLE_SHIFT 31
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/* AHG modes */
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/*
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* Be aware the ordering and values
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* for SDMA_AHG_APPLY_UPDATE[123]
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* are assumed in generating a skip
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* count in submit_tx() in sdma.c
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*/
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#define SDMA_AHG_NO_AHG 0
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#define SDMA_AHG_COPY 1
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#define SDMA_AHG_APPLY_UPDATE1 2
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#define SDMA_AHG_APPLY_UPDATE2 3
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#define SDMA_AHG_APPLY_UPDATE3 4
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/*
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* Bits defined in the send DMA descriptor.
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*/
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#define SDMA_DESC0_FIRST_DESC_FLAG BIT_ULL(63)
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#define SDMA_DESC0_LAST_DESC_FLAG BIT_ULL(62)
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#define SDMA_DESC0_BYTE_COUNT_SHIFT 48
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#define SDMA_DESC0_BYTE_COUNT_WIDTH 14
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#define SDMA_DESC0_BYTE_COUNT_MASK \
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((1ULL << SDMA_DESC0_BYTE_COUNT_WIDTH) - 1)
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#define SDMA_DESC0_BYTE_COUNT_SMASK \
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(SDMA_DESC0_BYTE_COUNT_MASK << SDMA_DESC0_BYTE_COUNT_SHIFT)
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#define SDMA_DESC0_PHY_ADDR_SHIFT 0
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#define SDMA_DESC0_PHY_ADDR_WIDTH 48
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#define SDMA_DESC0_PHY_ADDR_MASK \
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((1ULL << SDMA_DESC0_PHY_ADDR_WIDTH) - 1)
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#define SDMA_DESC0_PHY_ADDR_SMASK \
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(SDMA_DESC0_PHY_ADDR_MASK << SDMA_DESC0_PHY_ADDR_SHIFT)
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#define SDMA_DESC1_HEADER_UPDATE1_SHIFT 32
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#define SDMA_DESC1_HEADER_UPDATE1_WIDTH 32
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#define SDMA_DESC1_HEADER_UPDATE1_MASK \
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((1ULL << SDMA_DESC1_HEADER_UPDATE1_WIDTH) - 1)
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#define SDMA_DESC1_HEADER_UPDATE1_SMASK \
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(SDMA_DESC1_HEADER_UPDATE1_MASK << SDMA_DESC1_HEADER_UPDATE1_SHIFT)
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#define SDMA_DESC1_HEADER_MODE_SHIFT 13
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#define SDMA_DESC1_HEADER_MODE_WIDTH 3
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#define SDMA_DESC1_HEADER_MODE_MASK \
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((1ULL << SDMA_DESC1_HEADER_MODE_WIDTH) - 1)
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#define SDMA_DESC1_HEADER_MODE_SMASK \
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(SDMA_DESC1_HEADER_MODE_MASK << SDMA_DESC1_HEADER_MODE_SHIFT)
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#define SDMA_DESC1_HEADER_INDEX_SHIFT 8
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#define SDMA_DESC1_HEADER_INDEX_WIDTH 5
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#define SDMA_DESC1_HEADER_INDEX_MASK \
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((1ULL << SDMA_DESC1_HEADER_INDEX_WIDTH) - 1)
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#define SDMA_DESC1_HEADER_INDEX_SMASK \
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(SDMA_DESC1_HEADER_INDEX_MASK << SDMA_DESC1_HEADER_INDEX_SHIFT)
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#define SDMA_DESC1_HEADER_DWS_SHIFT 4
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#define SDMA_DESC1_HEADER_DWS_WIDTH 4
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#define SDMA_DESC1_HEADER_DWS_MASK \
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((1ULL << SDMA_DESC1_HEADER_DWS_WIDTH) - 1)
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#define SDMA_DESC1_HEADER_DWS_SMASK \
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(SDMA_DESC1_HEADER_DWS_MASK << SDMA_DESC1_HEADER_DWS_SHIFT)
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#define SDMA_DESC1_GENERATION_SHIFT 2
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#define SDMA_DESC1_GENERATION_WIDTH 2
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#define SDMA_DESC1_GENERATION_MASK \
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((1ULL << SDMA_DESC1_GENERATION_WIDTH) - 1)
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#define SDMA_DESC1_GENERATION_SMASK \
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(SDMA_DESC1_GENERATION_MASK << SDMA_DESC1_GENERATION_SHIFT)
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#define SDMA_DESC1_INT_REQ_FLAG BIT_ULL(1)
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#define SDMA_DESC1_HEAD_TO_HOST_FLAG BIT_ULL(0)
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enum sdma_states {
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sdma_state_s00_hw_down,
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sdma_state_s10_hw_start_up_halt_wait,
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sdma_state_s15_hw_start_up_clean_wait,
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sdma_state_s20_idle,
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sdma_state_s30_sw_clean_up_wait,
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sdma_state_s40_hw_clean_up_wait,
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sdma_state_s50_hw_halt_wait,
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sdma_state_s60_idle_halt_wait,
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sdma_state_s80_hw_freeze,
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sdma_state_s82_freeze_sw_clean,
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sdma_state_s99_running,
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};
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enum sdma_events {
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sdma_event_e00_go_hw_down,
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sdma_event_e10_go_hw_start,
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sdma_event_e15_hw_halt_done,
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sdma_event_e25_hw_clean_up_done,
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sdma_event_e30_go_running,
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sdma_event_e40_sw_cleaned,
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sdma_event_e50_hw_cleaned,
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sdma_event_e60_hw_halted,
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sdma_event_e70_go_idle,
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sdma_event_e80_hw_freeze,
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sdma_event_e81_hw_frozen,
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sdma_event_e82_hw_unfreeze,
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sdma_event_e85_link_down,
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sdma_event_e90_sw_halted,
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};
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struct sdma_set_state_action {
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unsigned op_enable:1;
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unsigned op_intenable:1;
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unsigned op_halt:1;
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unsigned op_cleanup:1;
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unsigned go_s99_running_tofalse:1;
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unsigned go_s99_running_totrue:1;
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};
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struct sdma_state {
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struct kref kref;
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struct completion comp;
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enum sdma_states current_state;
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unsigned current_op;
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unsigned go_s99_running;
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/* debugging/development */
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enum sdma_states previous_state;
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unsigned previous_op;
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enum sdma_events last_event;
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};
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/**
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* DOC: sdma exported routines
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*
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* These sdma routines fit into three categories:
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* - The SDMA API for building and submitting packets
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* to the ring
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*
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* - Initialization and tear down routines to buildup
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* and tear down SDMA
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*
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* - ISR entrances to handle interrupts, state changes
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* and errors
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*/
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/**
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* DOC: sdma PSM/verbs API
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*
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* The sdma API is designed to be used by both PSM
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* and verbs to supply packets to the SDMA ring.
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*
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* The usage of the API is as follows:
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*
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* Embed a struct iowait in the QP or
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* PQ. The iowait should be initialized with a
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* call to iowait_init().
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*
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* The user of the API should create an allocation method
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* for their version of the txreq. slabs, pre-allocated lists,
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* and dma pools can be used. Once the user's overload of
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* the sdma_txreq has been allocated, the sdma_txreq member
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* must be initialized with sdma_txinit() or sdma_txinit_ahg().
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*
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* The txreq must be declared with the sdma_txreq first.
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*
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* The tx request, once initialized, is manipulated with calls to
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* sdma_txadd_daddr(), sdma_txadd_page(), or sdma_txadd_kvaddr()
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* for each disjoint memory location. It is the user's responsibility
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* to understand the packet boundaries and page boundaries to do the
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* appropriate number of sdma_txadd_* calls.. The user
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* must be prepared to deal with failures from these routines due to
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* either memory allocation or dma_mapping failures.
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*
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* The mapping specifics for each memory location are recorded
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* in the tx. Memory locations added with sdma_txadd_page()
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* and sdma_txadd_kvaddr() are automatically mapped when added
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* to the tx and nmapped as part of the progress processing in the
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* SDMA interrupt handling.
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*
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* sdma_txadd_daddr() is used to add an dma_addr_t memory to the
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* tx. An example of a use case would be a pre-allocated
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* set of headers allocated via dma_pool_alloc() or
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* dma_alloc_coherent(). For these memory locations, it
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* is the responsibility of the user to handle that unmapping.
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* (This would usually be at an unload or job termination.)
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*
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* The routine sdma_send_txreq() is used to submit
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* a tx to the ring after the appropriate number of
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* sdma_txadd_* have been done.
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*
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* If it is desired to send a burst of sdma_txreqs, sdma_send_txlist()
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* can be used to submit a list of packets.
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*
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* The user is free to use the link overhead in the struct sdma_txreq as
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* long as the tx isn't in flight.
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*
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* The extreme degenerate case of the number of descriptors
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* exceeding the ring size is automatically handled as
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* memory locations are added. An overflow of the descriptor
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* array that is part of the sdma_txreq is also automatically
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* handled.
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*
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*/
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/**
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* DOC: Infrastructure calls
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*
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* sdma_init() is used to initialize data structures and
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* CSRs for the desired number of SDMA engines.
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*
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* sdma_start() is used to kick the SDMA engines initialized
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* with sdma_init(). Interrupts must be enabled at this
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* point since aspects of the state machine are interrupt
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* driven.
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*
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* sdma_engine_error() and sdma_engine_interrupt() are
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* entrances for interrupts.
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*
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* sdma_map_init() is for the management of the mapping
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* table when the number of vls is changed.
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*
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*/
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/*
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* struct hw_sdma_desc - raw 128 bit SDMA descriptor
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*
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* This is the raw descriptor in the SDMA ring
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*/
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struct hw_sdma_desc {
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/* private: don't use directly */
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__le64 qw[2];
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};
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/**
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* struct sdma_engine - Data pertaining to each SDMA engine.
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* @dd: a back-pointer to the device data
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* @ppd: per port back-pointer
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* @imask: mask for irq manipulation
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* @idle_mask: mask for determining if an interrupt is due to sdma_idle
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*
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* This structure has the state for each sdma_engine.
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*
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* Accessing to non public fields are not supported
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* since the private members are subject to change.
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*/
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struct sdma_engine {
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/* read mostly */
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struct hfi1_devdata *dd;
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struct hfi1_pportdata *ppd;
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/* private: */
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void __iomem *tail_csr;
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u64 imask; /* clear interrupt mask */
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u64 idle_mask;
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u64 progress_mask;
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u64 int_mask;
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/* private: */
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volatile __le64 *head_dma; /* DMA'ed by chip */
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/* private: */
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dma_addr_t head_phys;
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/* private: */
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struct hw_sdma_desc *descq;
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/* private: */
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unsigned descq_full_count;
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struct sdma_txreq **tx_ring;
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/* private: */
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dma_addr_t descq_phys;
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/* private */
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u32 sdma_mask;
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/* private */
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struct sdma_state state;
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/* private */
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int cpu;
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/* private: */
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u8 sdma_shift;
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/* private: */
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u8 this_idx; /* zero relative engine */
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/* protect changes to senddmactrl shadow */
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spinlock_t senddmactrl_lock;
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/* private: */
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u64 p_senddmactrl; /* shadow per-engine SendDmaCtrl */
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/* read/write using tail_lock */
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spinlock_t tail_lock ____cacheline_aligned_in_smp;
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#ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
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/* private: */
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u64 tail_sn;
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#endif
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/* private: */
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u32 descq_tail;
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/* private: */
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unsigned long ahg_bits;
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/* private: */
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u16 desc_avail;
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/* private: */
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u16 tx_tail;
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/* private: */
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u16 descq_cnt;
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/* read/write using head_lock */
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/* private: */
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seqlock_t head_lock ____cacheline_aligned_in_smp;
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#ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
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/* private: */
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u64 head_sn;
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#endif
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/* private: */
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u32 descq_head;
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/* private: */
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u16 tx_head;
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/* private: */
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u64 last_status;
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/* private */
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u64 err_cnt;
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/* private */
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u64 sdma_int_cnt;
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u64 idle_int_cnt;
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u64 progress_int_cnt;
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/* private: */
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seqlock_t waitlock;
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struct list_head dmawait;
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/* CONFIG SDMA for now, just blindly duplicate */
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/* private: */
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struct tasklet_struct sdma_hw_clean_up_task
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____cacheline_aligned_in_smp;
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/* private: */
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struct tasklet_struct sdma_sw_clean_up_task
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____cacheline_aligned_in_smp;
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/* private: */
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struct work_struct err_halt_worker;
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/* private */
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struct timer_list err_progress_check_timer;
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u32 progress_check_head;
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/* private: */
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struct work_struct flush_worker;
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/* protect flush list */
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spinlock_t flushlist_lock;
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/* private: */
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struct list_head flushlist;
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struct cpumask cpu_mask;
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struct kobject kobj;
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u32 msix_intr;
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};
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int sdma_init(struct hfi1_devdata *dd, u8 port);
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void sdma_start(struct hfi1_devdata *dd);
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void sdma_exit(struct hfi1_devdata *dd);
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void sdma_clean(struct hfi1_devdata *dd, size_t num_engines);
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void sdma_all_running(struct hfi1_devdata *dd);
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void sdma_all_idle(struct hfi1_devdata *dd);
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void sdma_freeze_notify(struct hfi1_devdata *dd, int go_idle);
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void sdma_freeze(struct hfi1_devdata *dd);
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void sdma_unfreeze(struct hfi1_devdata *dd);
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void sdma_wait(struct hfi1_devdata *dd);
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/**
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* sdma_empty() - idle engine test
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* @engine: sdma engine
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*
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* Currently used by verbs as a latency optimization.
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*
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* Return:
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* 1 - empty, 0 - non-empty
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*/
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static inline int sdma_empty(struct sdma_engine *sde)
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{
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return sde->descq_tail == sde->descq_head;
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}
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static inline u16 sdma_descq_freecnt(struct sdma_engine *sde)
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{
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return sde->descq_cnt -
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(sde->descq_tail -
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READ_ONCE(sde->descq_head)) - 1;
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}
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static inline u16 sdma_descq_inprocess(struct sdma_engine *sde)
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{
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return sde->descq_cnt - sdma_descq_freecnt(sde);
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}
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/*
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* Either head_lock or tail lock required to see
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* a steady state.
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*/
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static inline int __sdma_running(struct sdma_engine *engine)
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{
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return engine->state.current_state == sdma_state_s99_running;
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}
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/**
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* sdma_running() - state suitability test
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* @engine: sdma engine
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*
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* sdma_running probes the internal state to determine if it is suitable
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* for submitting packets.
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*
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* Return:
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* 1 - ok to submit, 0 - not ok to submit
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*
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*/
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static inline int sdma_running(struct sdma_engine *engine)
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{
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&engine->tail_lock, flags);
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ret = __sdma_running(engine);
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spin_unlock_irqrestore(&engine->tail_lock, flags);
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return ret;
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}
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void _sdma_txreq_ahgadd(
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struct sdma_txreq *tx,
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u8 num_ahg,
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u8 ahg_entry,
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u32 *ahg,
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u8 ahg_hlen);
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/**
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* sdma_txinit_ahg() - initialize an sdma_txreq struct with AHG
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* @tx: tx request to initialize
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* @flags: flags to key last descriptor additions
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* @tlen: total packet length (pbc + headers + data)
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* @ahg_entry: ahg entry to use (0 - 31)
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* @num_ahg: ahg descriptor for first descriptor (0 - 9)
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* @ahg: array of AHG descriptors (up to 9 entries)
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* @ahg_hlen: number of bytes from ASIC entry to use
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* @cb: callback
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*
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* The allocation of the sdma_txreq and it enclosing structure is user
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* dependent. This routine must be called to initialize the user independent
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* fields.
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*
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* The currently supported flags are SDMA_TXREQ_F_URGENT,
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* SDMA_TXREQ_F_AHG_COPY, and SDMA_TXREQ_F_USE_AHG.
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*
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* SDMA_TXREQ_F_URGENT is used for latency sensitive situations where the
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* completion is desired as soon as possible.
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*
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* SDMA_TXREQ_F_AHG_COPY causes the header in the first descriptor to be
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* copied to chip entry. SDMA_TXREQ_F_USE_AHG causes the code to add in
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* the AHG descriptors into the first 1 to 3 descriptors.
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|
*
|
|
* Completions of submitted requests can be gotten on selected
|
|
* txreqs by giving a completion routine callback to sdma_txinit() or
|
|
* sdma_txinit_ahg(). The environment in which the callback runs
|
|
* can be from an ISR, a tasklet, or a thread, so no sleeping
|
|
* kernel routines can be used. Aspects of the sdma ring may
|
|
* be locked so care should be taken with locking.
|
|
*
|
|
* The callback pointer can be NULL to avoid any callback for the packet
|
|
* being submitted. The callback will be provided this tx, a status, and a flag.
|
|
*
|
|
* The status will be one of SDMA_TXREQ_S_OK, SDMA_TXREQ_S_SENDERROR,
|
|
* SDMA_TXREQ_S_ABORTED, or SDMA_TXREQ_S_SHUTDOWN.
|
|
*
|
|
* The flag, if the is the iowait had been used, indicates the iowait
|
|
* sdma_busy count has reached zero.
|
|
*
|
|
* user data portion of tlen should be precise. The sdma_txadd_* entrances
|
|
* will pad with a descriptor references 1 - 3 bytes when the number of bytes
|
|
* specified in tlen have been supplied to the sdma_txreq.
|
|
*
|
|
* ahg_hlen is used to determine the number of on-chip entry bytes to
|
|
* use as the header. This is for cases where the stored header is
|
|
* larger than the header to be used in a packet. This is typical
|
|
* for verbs where an RDMA_WRITE_FIRST is larger than the packet in
|
|
* and RDMA_WRITE_MIDDLE.
|
|
*
|
|
*/
|
|
static inline int sdma_txinit_ahg(
|
|
struct sdma_txreq *tx,
|
|
u16 flags,
|
|
u16 tlen,
|
|
u8 ahg_entry,
|
|
u8 num_ahg,
|
|
u32 *ahg,
|
|
u8 ahg_hlen,
|
|
void (*cb)(struct sdma_txreq *, int))
|
|
{
|
|
if (tlen == 0)
|
|
return -ENODATA;
|
|
if (tlen > MAX_SDMA_PKT_SIZE)
|
|
return -EMSGSIZE;
|
|
tx->desc_limit = ARRAY_SIZE(tx->descs);
|
|
tx->descp = &tx->descs[0];
|
|
INIT_LIST_HEAD(&tx->list);
|
|
tx->num_desc = 0;
|
|
tx->flags = flags;
|
|
tx->complete = cb;
|
|
tx->coalesce_buf = NULL;
|
|
tx->wait = NULL;
|
|
tx->packet_len = tlen;
|
|
tx->tlen = tx->packet_len;
|
|
tx->descs[0].qw[0] = SDMA_DESC0_FIRST_DESC_FLAG;
|
|
tx->descs[0].qw[1] = 0;
|
|
if (flags & SDMA_TXREQ_F_AHG_COPY)
|
|
tx->descs[0].qw[1] |=
|
|
(((u64)ahg_entry & SDMA_DESC1_HEADER_INDEX_MASK)
|
|
<< SDMA_DESC1_HEADER_INDEX_SHIFT) |
|
|
(((u64)SDMA_AHG_COPY & SDMA_DESC1_HEADER_MODE_MASK)
|
|
<< SDMA_DESC1_HEADER_MODE_SHIFT);
|
|
else if (flags & SDMA_TXREQ_F_USE_AHG && num_ahg)
|
|
_sdma_txreq_ahgadd(tx, num_ahg, ahg_entry, ahg, ahg_hlen);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* sdma_txinit() - initialize an sdma_txreq struct (no AHG)
|
|
* @tx: tx request to initialize
|
|
* @flags: flags to key last descriptor additions
|
|
* @tlen: total packet length (pbc + headers + data)
|
|
* @cb: callback pointer
|
|
*
|
|
* The allocation of the sdma_txreq and it enclosing structure is user
|
|
* dependent. This routine must be called to initialize the user
|
|
* independent fields.
|
|
*
|
|
* The currently supported flags is SDMA_TXREQ_F_URGENT.
|
|
*
|
|
* SDMA_TXREQ_F_URGENT is used for latency sensitive situations where the
|
|
* completion is desired as soon as possible.
|
|
*
|
|
* Completions of submitted requests can be gotten on selected
|
|
* txreqs by giving a completion routine callback to sdma_txinit() or
|
|
* sdma_txinit_ahg(). The environment in which the callback runs
|
|
* can be from an ISR, a tasklet, or a thread, so no sleeping
|
|
* kernel routines can be used. The head size of the sdma ring may
|
|
* be locked so care should be taken with locking.
|
|
*
|
|
* The callback pointer can be NULL to avoid any callback for the packet
|
|
* being submitted.
|
|
*
|
|
* The callback, if non-NULL, will be provided this tx and a status. The
|
|
* status will be one of SDMA_TXREQ_S_OK, SDMA_TXREQ_S_SENDERROR,
|
|
* SDMA_TXREQ_S_ABORTED, or SDMA_TXREQ_S_SHUTDOWN.
|
|
*
|
|
*/
|
|
static inline int sdma_txinit(
|
|
struct sdma_txreq *tx,
|
|
u16 flags,
|
|
u16 tlen,
|
|
void (*cb)(struct sdma_txreq *, int))
|
|
{
|
|
return sdma_txinit_ahg(tx, flags, tlen, 0, 0, NULL, 0, cb);
|
|
}
|
|
|
|
/* helpers - don't use */
|
|
static inline int sdma_mapping_type(struct sdma_desc *d)
|
|
{
|
|
return (d->qw[1] & SDMA_DESC1_GENERATION_SMASK)
|
|
>> SDMA_DESC1_GENERATION_SHIFT;
|
|
}
|
|
|
|
static inline size_t sdma_mapping_len(struct sdma_desc *d)
|
|
{
|
|
return (d->qw[0] & SDMA_DESC0_BYTE_COUNT_SMASK)
|
|
>> SDMA_DESC0_BYTE_COUNT_SHIFT;
|
|
}
|
|
|
|
static inline dma_addr_t sdma_mapping_addr(struct sdma_desc *d)
|
|
{
|
|
return (d->qw[0] & SDMA_DESC0_PHY_ADDR_SMASK)
|
|
>> SDMA_DESC0_PHY_ADDR_SHIFT;
|
|
}
|
|
|
|
static inline void make_tx_sdma_desc(
|
|
struct sdma_txreq *tx,
|
|
int type,
|
|
dma_addr_t addr,
|
|
size_t len)
|
|
{
|
|
struct sdma_desc *desc = &tx->descp[tx->num_desc];
|
|
|
|
if (!tx->num_desc) {
|
|
/* qw[0] zero; qw[1] first, ahg mode already in from init */
|
|
desc->qw[1] |= ((u64)type & SDMA_DESC1_GENERATION_MASK)
|
|
<< SDMA_DESC1_GENERATION_SHIFT;
|
|
} else {
|
|
desc->qw[0] = 0;
|
|
desc->qw[1] = ((u64)type & SDMA_DESC1_GENERATION_MASK)
|
|
<< SDMA_DESC1_GENERATION_SHIFT;
|
|
}
|
|
desc->qw[0] |= (((u64)addr & SDMA_DESC0_PHY_ADDR_MASK)
|
|
<< SDMA_DESC0_PHY_ADDR_SHIFT) |
|
|
(((u64)len & SDMA_DESC0_BYTE_COUNT_MASK)
|
|
<< SDMA_DESC0_BYTE_COUNT_SHIFT);
|
|
}
|
|
|
|
/* helper to extend txreq */
|
|
int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx,
|
|
int type, void *kvaddr, struct page *page,
|
|
unsigned long offset, u16 len);
|
|
int _pad_sdma_tx_descs(struct hfi1_devdata *, struct sdma_txreq *);
|
|
void __sdma_txclean(struct hfi1_devdata *, struct sdma_txreq *);
|
|
|
|
static inline void sdma_txclean(struct hfi1_devdata *dd, struct sdma_txreq *tx)
|
|
{
|
|
if (tx->num_desc)
|
|
__sdma_txclean(dd, tx);
|
|
}
|
|
|
|
/* helpers used by public routines */
|
|
static inline void _sdma_close_tx(struct hfi1_devdata *dd,
|
|
struct sdma_txreq *tx)
|
|
{
|
|
tx->descp[tx->num_desc].qw[0] |=
|
|
SDMA_DESC0_LAST_DESC_FLAG;
|
|
tx->descp[tx->num_desc].qw[1] |=
|
|
dd->default_desc1;
|
|
if (tx->flags & SDMA_TXREQ_F_URGENT)
|
|
tx->descp[tx->num_desc].qw[1] |=
|
|
(SDMA_DESC1_HEAD_TO_HOST_FLAG |
|
|
SDMA_DESC1_INT_REQ_FLAG);
|
|
}
|
|
|
|
static inline int _sdma_txadd_daddr(
|
|
struct hfi1_devdata *dd,
|
|
int type,
|
|
struct sdma_txreq *tx,
|
|
dma_addr_t addr,
|
|
u16 len)
|
|
{
|
|
int rval = 0;
|
|
|
|
make_tx_sdma_desc(
|
|
tx,
|
|
type,
|
|
addr, len);
|
|
WARN_ON(len > tx->tlen);
|
|
tx->tlen -= len;
|
|
/* special cases for last */
|
|
if (!tx->tlen) {
|
|
if (tx->packet_len & (sizeof(u32) - 1)) {
|
|
rval = _pad_sdma_tx_descs(dd, tx);
|
|
if (rval)
|
|
return rval;
|
|
} else {
|
|
_sdma_close_tx(dd, tx);
|
|
}
|
|
}
|
|
tx->num_desc++;
|
|
return rval;
|
|
}
|
|
|
|
/**
|
|
* sdma_txadd_page() - add a page to the sdma_txreq
|
|
* @dd: the device to use for mapping
|
|
* @tx: tx request to which the page is added
|
|
* @page: page to map
|
|
* @offset: offset within the page
|
|
* @len: length in bytes
|
|
*
|
|
* This is used to add a page/offset/length descriptor.
|
|
*
|
|
* The mapping/unmapping of the page/offset/len is automatically handled.
|
|
*
|
|
* Return:
|
|
* 0 - success, -ENOSPC - mapping fail, -ENOMEM - couldn't
|
|
* extend/coalesce descriptor array
|
|
*/
|
|
static inline int sdma_txadd_page(
|
|
struct hfi1_devdata *dd,
|
|
struct sdma_txreq *tx,
|
|
struct page *page,
|
|
unsigned long offset,
|
|
u16 len)
|
|
{
|
|
dma_addr_t addr;
|
|
int rval;
|
|
|
|
if ((unlikely(tx->num_desc == tx->desc_limit))) {
|
|
rval = ext_coal_sdma_tx_descs(dd, tx, SDMA_MAP_PAGE,
|
|
NULL, page, offset, len);
|
|
if (rval <= 0)
|
|
return rval;
|
|
}
|
|
|
|
addr = dma_map_page(
|
|
&dd->pcidev->dev,
|
|
page,
|
|
offset,
|
|
len,
|
|
DMA_TO_DEVICE);
|
|
|
|
if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) {
|
|
__sdma_txclean(dd, tx);
|
|
return -ENOSPC;
|
|
}
|
|
|
|
return _sdma_txadd_daddr(
|
|
dd, SDMA_MAP_PAGE, tx, addr, len);
|
|
}
|
|
|
|
/**
|
|
* sdma_txadd_daddr() - add a dma address to the sdma_txreq
|
|
* @dd: the device to use for mapping
|
|
* @tx: sdma_txreq to which the page is added
|
|
* @addr: dma address mapped by caller
|
|
* @len: length in bytes
|
|
*
|
|
* This is used to add a descriptor for memory that is already dma mapped.
|
|
*
|
|
* In this case, there is no unmapping as part of the progress processing for
|
|
* this memory location.
|
|
*
|
|
* Return:
|
|
* 0 - success, -ENOMEM - couldn't extend descriptor array
|
|
*/
|
|
|
|
static inline int sdma_txadd_daddr(
|
|
struct hfi1_devdata *dd,
|
|
struct sdma_txreq *tx,
|
|
dma_addr_t addr,
|
|
u16 len)
|
|
{
|
|
int rval;
|
|
|
|
if ((unlikely(tx->num_desc == tx->desc_limit))) {
|
|
rval = ext_coal_sdma_tx_descs(dd, tx, SDMA_MAP_NONE,
|
|
NULL, NULL, 0, 0);
|
|
if (rval <= 0)
|
|
return rval;
|
|
}
|
|
|
|
return _sdma_txadd_daddr(dd, SDMA_MAP_NONE, tx, addr, len);
|
|
}
|
|
|
|
/**
|
|
* sdma_txadd_kvaddr() - add a kernel virtual address to sdma_txreq
|
|
* @dd: the device to use for mapping
|
|
* @tx: sdma_txreq to which the page is added
|
|
* @kvaddr: the kernel virtual address
|
|
* @len: length in bytes
|
|
*
|
|
* This is used to add a descriptor referenced by the indicated kvaddr and
|
|
* len.
|
|
*
|
|
* The mapping/unmapping of the kvaddr and len is automatically handled.
|
|
*
|
|
* Return:
|
|
* 0 - success, -ENOSPC - mapping fail, -ENOMEM - couldn't extend/coalesce
|
|
* descriptor array
|
|
*/
|
|
static inline int sdma_txadd_kvaddr(
|
|
struct hfi1_devdata *dd,
|
|
struct sdma_txreq *tx,
|
|
void *kvaddr,
|
|
u16 len)
|
|
{
|
|
dma_addr_t addr;
|
|
int rval;
|
|
|
|
if ((unlikely(tx->num_desc == tx->desc_limit))) {
|
|
rval = ext_coal_sdma_tx_descs(dd, tx, SDMA_MAP_SINGLE,
|
|
kvaddr, NULL, 0, len);
|
|
if (rval <= 0)
|
|
return rval;
|
|
}
|
|
|
|
addr = dma_map_single(
|
|
&dd->pcidev->dev,
|
|
kvaddr,
|
|
len,
|
|
DMA_TO_DEVICE);
|
|
|
|
if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) {
|
|
__sdma_txclean(dd, tx);
|
|
return -ENOSPC;
|
|
}
|
|
|
|
return _sdma_txadd_daddr(
|
|
dd, SDMA_MAP_SINGLE, tx, addr, len);
|
|
}
|
|
|
|
struct iowait_work;
|
|
|
|
int sdma_send_txreq(struct sdma_engine *sde,
|
|
struct iowait_work *wait,
|
|
struct sdma_txreq *tx,
|
|
bool pkts_sent);
|
|
int sdma_send_txlist(struct sdma_engine *sde,
|
|
struct iowait_work *wait,
|
|
struct list_head *tx_list,
|
|
u16 *count_out);
|
|
|
|
int sdma_ahg_alloc(struct sdma_engine *sde);
|
|
void sdma_ahg_free(struct sdma_engine *sde, int ahg_index);
|
|
|
|
/**
|
|
* sdma_build_ahg - build ahg descriptor
|
|
* @data
|
|
* @dwindex
|
|
* @startbit
|
|
* @bits
|
|
*
|
|
* Build and return a 32 bit descriptor.
|
|
*/
|
|
static inline u32 sdma_build_ahg_descriptor(
|
|
u16 data,
|
|
u8 dwindex,
|
|
u8 startbit,
|
|
u8 bits)
|
|
{
|
|
return (u32)(1UL << SDMA_AHG_UPDATE_ENABLE_SHIFT |
|
|
((startbit & SDMA_AHG_FIELD_START_MASK) <<
|
|
SDMA_AHG_FIELD_START_SHIFT) |
|
|
((bits & SDMA_AHG_FIELD_LEN_MASK) <<
|
|
SDMA_AHG_FIELD_LEN_SHIFT) |
|
|
((dwindex & SDMA_AHG_INDEX_MASK) <<
|
|
SDMA_AHG_INDEX_SHIFT) |
|
|
((data & SDMA_AHG_VALUE_MASK) <<
|
|
SDMA_AHG_VALUE_SHIFT));
|
|
}
|
|
|
|
/**
|
|
* sdma_progress - use seq number of detect head progress
|
|
* @sde: sdma_engine to check
|
|
* @seq: base seq count
|
|
* @tx: txreq for which we need to check descriptor availability
|
|
*
|
|
* This is used in the appropriate spot in the sleep routine
|
|
* to check for potential ring progress. This routine gets the
|
|
* seqcount before queuing the iowait structure for progress.
|
|
*
|
|
* If the seqcount indicates that progress needs to be checked,
|
|
* re-submission is detected by checking whether the descriptor
|
|
* queue has enough descriptor for the txreq.
|
|
*/
|
|
static inline unsigned sdma_progress(struct sdma_engine *sde, unsigned seq,
|
|
struct sdma_txreq *tx)
|
|
{
|
|
if (read_seqretry(&sde->head_lock, seq)) {
|
|
sde->desc_avail = sdma_descq_freecnt(sde);
|
|
if (tx->num_desc > sde->desc_avail)
|
|
return 0;
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* for use by interrupt handling */
|
|
void sdma_engine_error(struct sdma_engine *sde, u64 status);
|
|
void sdma_engine_interrupt(struct sdma_engine *sde, u64 status);
|
|
|
|
/*
|
|
*
|
|
* The diagram below details the relationship of the mapping structures
|
|
*
|
|
* Since the mapping now allows for non-uniform engines per vl, the
|
|
* number of engines for a vl is either the vl_engines[vl] or
|
|
* a computation based on num_sdma/num_vls:
|
|
*
|
|
* For example:
|
|
* nactual = vl_engines ? vl_engines[vl] : num_sdma/num_vls
|
|
*
|
|
* n = roundup to next highest power of 2 using nactual
|
|
*
|
|
* In the case where there are num_sdma/num_vls doesn't divide
|
|
* evenly, the extras are added from the last vl downward.
|
|
*
|
|
* For the case where n > nactual, the engines are assigned
|
|
* in a round robin fashion wrapping back to the first engine
|
|
* for a particular vl.
|
|
*
|
|
* dd->sdma_map
|
|
* | sdma_map_elem[0]
|
|
* | +--------------------+
|
|
* v | mask |
|
|
* sdma_vl_map |--------------------|
|
|
* +--------------------------+ | sde[0] -> eng 1 |
|
|
* | list (RCU) | |--------------------|
|
|
* |--------------------------| ->| sde[1] -> eng 2 |
|
|
* | mask | --/ |--------------------|
|
|
* |--------------------------| -/ | * |
|
|
* | actual_vls (max 8) | -/ |--------------------|
|
|
* |--------------------------| --/ | sde[n-1] -> eng n |
|
|
* | vls (max 8) | -/ +--------------------+
|
|
* |--------------------------| --/
|
|
* | map[0] |-/
|
|
* |--------------------------| +---------------------+
|
|
* | map[1] |--- | mask |
|
|
* |--------------------------| \---- |---------------------|
|
|
* | * | \-- | sde[0] -> eng 1+n |
|
|
* | * | \---- |---------------------|
|
|
* | * | \->| sde[1] -> eng 2+n |
|
|
* |--------------------------| |---------------------|
|
|
* | map[vls - 1] |- | * |
|
|
* +--------------------------+ \- |---------------------|
|
|
* \- | sde[m-1] -> eng m+n |
|
|
* \ +---------------------+
|
|
* \-
|
|
* \
|
|
* \- +----------------------+
|
|
* \- | mask |
|
|
* \ |----------------------|
|
|
* \- | sde[0] -> eng 1+m+n |
|
|
* \- |----------------------|
|
|
* >| sde[1] -> eng 2+m+n |
|
|
* |----------------------|
|
|
* | * |
|
|
* |----------------------|
|
|
* | sde[o-1] -> eng o+m+n|
|
|
* +----------------------+
|
|
*
|
|
*/
|
|
|
|
/**
|
|
* struct sdma_map_elem - mapping for a vl
|
|
* @mask - selector mask
|
|
* @sde - array of engines for this vl
|
|
*
|
|
* The mask is used to "mod" the selector
|
|
* to produce index into the trailing
|
|
* array of sdes.
|
|
*/
|
|
struct sdma_map_elem {
|
|
u32 mask;
|
|
struct sdma_engine *sde[];
|
|
};
|
|
|
|
/**
|
|
* struct sdma_map_el - mapping for a vl
|
|
* @engine_to_vl - map of an engine to a vl
|
|
* @list - rcu head for free callback
|
|
* @mask - vl mask to "mod" the vl to produce an index to map array
|
|
* @actual_vls - number of vls
|
|
* @vls - number of vls rounded to next power of 2
|
|
* @map - array of sdma_map_elem entries
|
|
*
|
|
* This is the parent mapping structure. The trailing
|
|
* members of the struct point to sdma_map_elem entries, which
|
|
* in turn point to an array of sde's for that vl.
|
|
*/
|
|
struct sdma_vl_map {
|
|
s8 engine_to_vl[TXE_NUM_SDMA_ENGINES];
|
|
struct rcu_head list;
|
|
u32 mask;
|
|
u8 actual_vls;
|
|
u8 vls;
|
|
struct sdma_map_elem *map[];
|
|
};
|
|
|
|
int sdma_map_init(
|
|
struct hfi1_devdata *dd,
|
|
u8 port,
|
|
u8 num_vls,
|
|
u8 *vl_engines);
|
|
|
|
/* slow path */
|
|
void _sdma_engine_progress_schedule(struct sdma_engine *sde);
|
|
|
|
/**
|
|
* sdma_engine_progress_schedule() - schedule progress on engine
|
|
* @sde: sdma_engine to schedule progress
|
|
*
|
|
* This is the fast path.
|
|
*
|
|
*/
|
|
static inline void sdma_engine_progress_schedule(
|
|
struct sdma_engine *sde)
|
|
{
|
|
if (!sde || sdma_descq_inprocess(sde) < (sde->descq_cnt / 8))
|
|
return;
|
|
_sdma_engine_progress_schedule(sde);
|
|
}
|
|
|
|
struct sdma_engine *sdma_select_engine_sc(
|
|
struct hfi1_devdata *dd,
|
|
u32 selector,
|
|
u8 sc5);
|
|
|
|
struct sdma_engine *sdma_select_engine_vl(
|
|
struct hfi1_devdata *dd,
|
|
u32 selector,
|
|
u8 vl);
|
|
|
|
struct sdma_engine *sdma_select_user_engine(struct hfi1_devdata *dd,
|
|
u32 selector, u8 vl);
|
|
ssize_t sdma_get_cpu_to_sde_map(struct sdma_engine *sde, char *buf);
|
|
ssize_t sdma_set_cpu_to_sde_map(struct sdma_engine *sde, const char *buf,
|
|
size_t count);
|
|
int sdma_engine_get_vl(struct sdma_engine *sde);
|
|
void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *);
|
|
void sdma_seqfile_dump_cpu_list(struct seq_file *s, struct hfi1_devdata *dd,
|
|
unsigned long cpuid);
|
|
|
|
#ifdef CONFIG_SDMA_VERBOSITY
|
|
void sdma_dumpstate(struct sdma_engine *);
|
|
#endif
|
|
static inline char *slashstrip(char *s)
|
|
{
|
|
char *r = s;
|
|
|
|
while (*s)
|
|
if (*s++ == '/')
|
|
r = s;
|
|
return r;
|
|
}
|
|
|
|
u16 sdma_get_descq_cnt(void);
|
|
|
|
extern uint mod_num_sdma;
|
|
|
|
void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid);
|
|
|
|
#endif
|