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![Mark Bloch](/assets/img/avatar_default.png)
Current code uses many different types when dealing with a port of a RDMA device: u8, unsigned int and u32. Switch to u32 to clean up the logic. This allows us to make (at least) the core view consistent and use the same type. Unfortunately not all places can be converted. Many uverbs functions expect port to be u8 so keep those places in order not to break UAPIs. HW/Spec defined values must also not be changed. With the switch to u32 we now can support devices with more than 255 ports. U32_MAX is reserved to make control logic a bit easier to deal with. As a device with U32_MAX ports probably isn't going to happen any time soon this seems like a non issue. When a device with more than 255 ports is created uverbs will report the RDMA device as having 255 ports as this is the max currently supported. The verbs interface is not changed yet because the IBTA spec limits the port size in too many places to be u8 and all applications that relies in verbs won't be able to cope with this change. At this stage, we are extending the interfaces that are using vendor channel solely Once the limitation is lifted mlx5 in switchdev mode will be able to have thousands of SFs created by the device. As the only instance of an RDMA device that reports more than 255 ports will be a representor device and it exposes itself as a RAW Ethernet only device CM/MAD/IPoIB and other ULPs aren't effected by this change and their sysfs/interfaces that are exposes to userspace can remain unchanged. While here cleanup some alignment issues and remove unneeded sanity checks (mainly in rdmavt), Link: https://lore.kernel.org/r/20210301070420.439400-1-leon@kernel.org Signed-off-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
376 lines
9.8 KiB
C
376 lines
9.8 KiB
C
/*
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* Copyright (c) 2004 Topspin Communications. All rights reserved.
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* Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <rdma/ib_verbs.h>
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#include <rdma/ib_cache.h>
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#include "mthca_dev.h"
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enum {
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MTHCA_RATE_TAVOR_FULL = 0,
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MTHCA_RATE_TAVOR_1X = 1,
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MTHCA_RATE_TAVOR_4X = 2,
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MTHCA_RATE_TAVOR_1X_DDR = 3
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};
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enum {
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MTHCA_RATE_MEMFREE_FULL = 0,
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MTHCA_RATE_MEMFREE_QUARTER = 1,
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MTHCA_RATE_MEMFREE_EIGHTH = 2,
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MTHCA_RATE_MEMFREE_HALF = 3
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};
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struct mthca_av {
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__be32 port_pd;
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u8 reserved1;
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u8 g_slid;
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__be16 dlid;
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u8 reserved2;
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u8 gid_index;
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u8 msg_sr;
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u8 hop_limit;
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__be32 sl_tclass_flowlabel;
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__be32 dgid[4];
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};
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static enum ib_rate memfree_rate_to_ib(u8 mthca_rate, u8 port_rate)
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{
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switch (mthca_rate) {
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case MTHCA_RATE_MEMFREE_EIGHTH:
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return mult_to_ib_rate(port_rate >> 3);
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case MTHCA_RATE_MEMFREE_QUARTER:
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return mult_to_ib_rate(port_rate >> 2);
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case MTHCA_RATE_MEMFREE_HALF:
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return mult_to_ib_rate(port_rate >> 1);
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case MTHCA_RATE_MEMFREE_FULL:
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default:
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return mult_to_ib_rate(port_rate);
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}
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}
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static enum ib_rate tavor_rate_to_ib(u8 mthca_rate, u8 port_rate)
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{
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switch (mthca_rate) {
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case MTHCA_RATE_TAVOR_1X: return IB_RATE_2_5_GBPS;
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case MTHCA_RATE_TAVOR_1X_DDR: return IB_RATE_5_GBPS;
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case MTHCA_RATE_TAVOR_4X: return IB_RATE_10_GBPS;
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default: return mult_to_ib_rate(port_rate);
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}
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}
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enum ib_rate mthca_rate_to_ib(struct mthca_dev *dev, u8 mthca_rate, u32 port)
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{
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if (mthca_is_memfree(dev)) {
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/* Handle old Arbel FW */
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if (dev->limits.stat_rate_support == 0x3 && mthca_rate)
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return IB_RATE_2_5_GBPS;
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return memfree_rate_to_ib(mthca_rate, dev->rate[port - 1]);
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} else
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return tavor_rate_to_ib(mthca_rate, dev->rate[port - 1]);
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}
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static u8 ib_rate_to_memfree(u8 req_rate, u8 cur_rate)
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{
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if (cur_rate <= req_rate)
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return 0;
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/*
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* Inter-packet delay (IPD) to get from rate X down to a rate
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* no more than Y is (X - 1) / Y.
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*/
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switch ((cur_rate - 1) / req_rate) {
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case 0: return MTHCA_RATE_MEMFREE_FULL;
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case 1: return MTHCA_RATE_MEMFREE_HALF;
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case 2:
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case 3: return MTHCA_RATE_MEMFREE_QUARTER;
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default: return MTHCA_RATE_MEMFREE_EIGHTH;
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}
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}
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static u8 ib_rate_to_tavor(u8 static_rate)
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{
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switch (static_rate) {
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case IB_RATE_2_5_GBPS: return MTHCA_RATE_TAVOR_1X;
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case IB_RATE_5_GBPS: return MTHCA_RATE_TAVOR_1X_DDR;
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case IB_RATE_10_GBPS: return MTHCA_RATE_TAVOR_4X;
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default: return MTHCA_RATE_TAVOR_FULL;
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}
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}
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u8 mthca_get_rate(struct mthca_dev *dev, int static_rate, u32 port)
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{
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u8 rate;
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if (!static_rate || ib_rate_to_mult(static_rate) >= dev->rate[port - 1])
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return 0;
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if (mthca_is_memfree(dev))
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rate = ib_rate_to_memfree(ib_rate_to_mult(static_rate),
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dev->rate[port - 1]);
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else
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rate = ib_rate_to_tavor(static_rate);
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if (!(dev->limits.stat_rate_support & (1 << rate)))
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rate = 1;
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return rate;
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}
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int mthca_create_ah(struct mthca_dev *dev,
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struct mthca_pd *pd,
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struct rdma_ah_attr *ah_attr,
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struct mthca_ah *ah)
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{
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u32 index = -1;
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struct mthca_av *av = NULL;
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ah->type = MTHCA_AH_PCI_POOL;
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if (mthca_is_memfree(dev)) {
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ah->av = kmalloc(sizeof *ah->av, GFP_ATOMIC);
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if (!ah->av)
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return -ENOMEM;
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ah->type = MTHCA_AH_KMALLOC;
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av = ah->av;
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} else if (!atomic_read(&pd->sqp_count) &&
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!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
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index = mthca_alloc(&dev->av_table.alloc);
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/* fall back to allocate in host memory */
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if (index == -1)
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goto on_hca_fail;
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av = kmalloc(sizeof *av, GFP_ATOMIC);
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if (!av)
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goto on_hca_fail;
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ah->type = MTHCA_AH_ON_HCA;
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ah->avdma = dev->av_table.ddr_av_base +
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index * MTHCA_AV_SIZE;
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}
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on_hca_fail:
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if (ah->type == MTHCA_AH_PCI_POOL) {
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ah->av = dma_pool_zalloc(dev->av_table.pool,
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GFP_ATOMIC, &ah->avdma);
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if (!ah->av)
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return -ENOMEM;
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av = ah->av;
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}
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ah->key = pd->ntmr.ibmr.lkey;
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av->port_pd = cpu_to_be32(pd->pd_num |
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(rdma_ah_get_port_num(ah_attr) << 24));
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av->g_slid = rdma_ah_get_path_bits(ah_attr);
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av->dlid = cpu_to_be16(rdma_ah_get_dlid(ah_attr));
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av->msg_sr = (3 << 4) | /* 2K message */
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mthca_get_rate(dev, rdma_ah_get_static_rate(ah_attr),
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rdma_ah_get_port_num(ah_attr));
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av->sl_tclass_flowlabel = cpu_to_be32(rdma_ah_get_sl(ah_attr) << 28);
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if (rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH) {
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const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
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av->g_slid |= 0x80;
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av->gid_index = (rdma_ah_get_port_num(ah_attr) - 1) *
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dev->limits.gid_table_len +
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grh->sgid_index;
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av->hop_limit = grh->hop_limit;
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av->sl_tclass_flowlabel |=
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cpu_to_be32((grh->traffic_class << 20) |
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grh->flow_label);
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memcpy(av->dgid, grh->dgid.raw, 16);
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} else {
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/* Arbel workaround -- low byte of GID must be 2 */
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av->dgid[3] = cpu_to_be32(2);
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}
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if (0) {
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int j;
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mthca_dbg(dev, "Created UDAV at %p/%08lx:\n",
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av, (unsigned long) ah->avdma);
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for (j = 0; j < 8; ++j)
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printk(KERN_DEBUG " [%2x] %08x\n",
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j * 4, be32_to_cpu(((__be32 *) av)[j]));
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}
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if (ah->type == MTHCA_AH_ON_HCA) {
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memcpy_toio(dev->av_table.av_map + index * MTHCA_AV_SIZE,
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av, MTHCA_AV_SIZE);
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kfree(av);
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}
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return 0;
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}
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int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah)
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{
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switch (ah->type) {
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case MTHCA_AH_ON_HCA:
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mthca_free(&dev->av_table.alloc,
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(ah->avdma - dev->av_table.ddr_av_base) /
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MTHCA_AV_SIZE);
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break;
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case MTHCA_AH_PCI_POOL:
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dma_pool_free(dev->av_table.pool, ah->av, ah->avdma);
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break;
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case MTHCA_AH_KMALLOC:
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kfree(ah->av);
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break;
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}
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return 0;
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}
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int mthca_ah_grh_present(struct mthca_ah *ah)
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{
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return !!(ah->av->g_slid & 0x80);
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}
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int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
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struct ib_ud_header *header)
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{
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if (ah->type == MTHCA_AH_ON_HCA)
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return -EINVAL;
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header->lrh.service_level = be32_to_cpu(ah->av->sl_tclass_flowlabel) >> 28;
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header->lrh.destination_lid = ah->av->dlid;
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header->lrh.source_lid = cpu_to_be16(ah->av->g_slid & 0x7f);
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if (mthca_ah_grh_present(ah)) {
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header->grh.traffic_class =
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(be32_to_cpu(ah->av->sl_tclass_flowlabel) >> 20) & 0xff;
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header->grh.flow_label =
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ah->av->sl_tclass_flowlabel & cpu_to_be32(0xfffff);
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header->grh.hop_limit = ah->av->hop_limit;
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header->grh.source_gid = ah->ibah.sgid_attr->gid;
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memcpy(header->grh.destination_gid.raw,
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ah->av->dgid, 16);
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}
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return 0;
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}
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int mthca_ah_query(struct ib_ah *ibah, struct rdma_ah_attr *attr)
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{
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struct mthca_ah *ah = to_mah(ibah);
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struct mthca_dev *dev = to_mdev(ibah->device);
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u32 port_num = be32_to_cpu(ah->av->port_pd) >> 24;
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/* Only implement for MAD and memfree ah for now. */
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if (ah->type == MTHCA_AH_ON_HCA)
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return -ENOSYS;
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memset(attr, 0, sizeof *attr);
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attr->type = ibah->type;
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rdma_ah_set_dlid(attr, be16_to_cpu(ah->av->dlid));
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rdma_ah_set_sl(attr, be32_to_cpu(ah->av->sl_tclass_flowlabel) >> 28);
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rdma_ah_set_port_num(attr, port_num);
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rdma_ah_set_static_rate(attr,
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mthca_rate_to_ib(dev, ah->av->msg_sr & 0x7,
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port_num));
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rdma_ah_set_path_bits(attr, ah->av->g_slid & 0x7F);
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if (mthca_ah_grh_present(ah)) {
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u32 tc_fl = be32_to_cpu(ah->av->sl_tclass_flowlabel);
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rdma_ah_set_grh(attr, NULL,
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tc_fl & 0xfffff,
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ah->av->gid_index &
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(dev->limits.gid_table_len - 1),
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ah->av->hop_limit,
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(tc_fl >> 20) & 0xff);
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rdma_ah_set_dgid_raw(attr, ah->av->dgid);
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}
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return 0;
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}
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int mthca_init_av_table(struct mthca_dev *dev)
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{
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int err;
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if (mthca_is_memfree(dev))
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return 0;
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err = mthca_alloc_init(&dev->av_table.alloc,
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dev->av_table.num_ddr_avs,
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dev->av_table.num_ddr_avs - 1,
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0);
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if (err)
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return err;
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dev->av_table.pool = dma_pool_create("mthca_av", &dev->pdev->dev,
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MTHCA_AV_SIZE,
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MTHCA_AV_SIZE, 0);
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if (!dev->av_table.pool)
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goto out_free_alloc;
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if (!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
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dev->av_table.av_map = ioremap(pci_resource_start(dev->pdev, 4) +
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dev->av_table.ddr_av_base -
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dev->ddr_start,
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dev->av_table.num_ddr_avs *
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MTHCA_AV_SIZE);
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if (!dev->av_table.av_map)
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goto out_free_pool;
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} else
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dev->av_table.av_map = NULL;
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return 0;
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out_free_pool:
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dma_pool_destroy(dev->av_table.pool);
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out_free_alloc:
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mthca_alloc_cleanup(&dev->av_table.alloc);
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return -ENOMEM;
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}
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void mthca_cleanup_av_table(struct mthca_dev *dev)
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{
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if (mthca_is_memfree(dev))
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return;
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if (dev->av_table.av_map)
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iounmap(dev->av_table.av_map);
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dma_pool_destroy(dev->av_table.pool);
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mthca_alloc_cleanup(&dev->av_table.alloc);
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}
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