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![Allen Pais](/assets/img/avatar_default.png)
In preparation for unconditionally passing the struct tasklet_struct pointer to all tasklet callbacks, switch to using the new tasklet_setup() and from_tasklet() to pass the tasklet pointer explicitly. Link: https://lore.kernel.org/r/20200903060637.424458-5-allen.lkml@gmail.com Signed-off-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Allen Pais <allen.lkml@gmail.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
999 lines
26 KiB
C
999 lines
26 KiB
C
/*
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* Copyright (c) 2012 Intel Corporation. All rights reserved.
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* Copyright (c) 2007 - 2012 QLogic Corporation. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/spinlock.h>
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#include <linux/netdevice.h>
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#include <linux/moduleparam.h>
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#include "qib.h"
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#include "qib_common.h"
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/* default pio off, sdma on */
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static ushort sdma_descq_cnt = 256;
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module_param_named(sdma_descq_cnt, sdma_descq_cnt, ushort, S_IRUGO);
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MODULE_PARM_DESC(sdma_descq_cnt, "Number of SDMA descq entries");
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/*
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* Bits defined in the send DMA descriptor.
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*/
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#define SDMA_DESC_LAST (1ULL << 11)
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#define SDMA_DESC_FIRST (1ULL << 12)
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#define SDMA_DESC_DMA_HEAD (1ULL << 13)
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#define SDMA_DESC_USE_LARGE_BUF (1ULL << 14)
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#define SDMA_DESC_INTR (1ULL << 15)
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#define SDMA_DESC_COUNT_LSB 16
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#define SDMA_DESC_GEN_LSB 30
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/* declare all statics here rather than keep sorting */
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static int alloc_sdma(struct qib_pportdata *);
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static void sdma_complete(struct kref *);
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static void sdma_finalput(struct qib_sdma_state *);
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static void sdma_get(struct qib_sdma_state *);
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static void sdma_put(struct qib_sdma_state *);
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static void sdma_set_state(struct qib_pportdata *, enum qib_sdma_states);
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static void sdma_start_sw_clean_up(struct qib_pportdata *);
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static void sdma_sw_clean_up_task(struct tasklet_struct *);
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static void unmap_desc(struct qib_pportdata *, unsigned);
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static void sdma_get(struct qib_sdma_state *ss)
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{
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kref_get(&ss->kref);
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}
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static void sdma_complete(struct kref *kref)
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{
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struct qib_sdma_state *ss =
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container_of(kref, struct qib_sdma_state, kref);
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complete(&ss->comp);
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}
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static void sdma_put(struct qib_sdma_state *ss)
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{
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kref_put(&ss->kref, sdma_complete);
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}
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static void sdma_finalput(struct qib_sdma_state *ss)
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{
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sdma_put(ss);
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wait_for_completion(&ss->comp);
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}
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/*
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* Complete all the sdma requests on the active list, in the correct
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* order, and with appropriate processing. Called when cleaning up
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* after sdma shutdown, and when new sdma requests are submitted for
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* a link that is down. This matches what is done for requests
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* that complete normally, it's just the full list.
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*
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* Must be called with sdma_lock held
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*/
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static void clear_sdma_activelist(struct qib_pportdata *ppd)
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{
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struct qib_sdma_txreq *txp, *txp_next;
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list_for_each_entry_safe(txp, txp_next, &ppd->sdma_activelist, list) {
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list_del_init(&txp->list);
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if (txp->flags & QIB_SDMA_TXREQ_F_FREEDESC) {
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unsigned idx;
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idx = txp->start_idx;
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while (idx != txp->next_descq_idx) {
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unmap_desc(ppd, idx);
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if (++idx == ppd->sdma_descq_cnt)
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idx = 0;
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}
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}
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if (txp->callback)
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(*txp->callback)(txp, QIB_SDMA_TXREQ_S_ABORTED);
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}
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}
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static void sdma_sw_clean_up_task(struct tasklet_struct *t)
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{
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struct qib_pportdata *ppd = from_tasklet(ppd, t,
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sdma_sw_clean_up_task);
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unsigned long flags;
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spin_lock_irqsave(&ppd->sdma_lock, flags);
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/*
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* At this point, the following should always be true:
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* - We are halted, so no more descriptors are getting retired.
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* - We are not running, so no one is submitting new work.
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* - Only we can send the e40_sw_cleaned, so we can't start
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* running again until we say so. So, the active list and
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* descq are ours to play with.
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*/
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/* Process all retired requests. */
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qib_sdma_make_progress(ppd);
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clear_sdma_activelist(ppd);
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/*
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* Resync count of added and removed. It is VERY important that
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* sdma_descq_removed NEVER decrement - user_sdma depends on it.
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*/
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ppd->sdma_descq_removed = ppd->sdma_descq_added;
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/*
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* Reset our notion of head and tail.
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* Note that the HW registers will be reset when switching states
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* due to calling __qib_sdma_process_event() below.
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*/
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ppd->sdma_descq_tail = 0;
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ppd->sdma_descq_head = 0;
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ppd->sdma_head_dma[0] = 0;
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ppd->sdma_generation = 0;
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__qib_sdma_process_event(ppd, qib_sdma_event_e40_sw_cleaned);
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spin_unlock_irqrestore(&ppd->sdma_lock, flags);
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}
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/*
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* This is called when changing to state qib_sdma_state_s10_hw_start_up_wait
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* as a result of send buffer errors or send DMA descriptor errors.
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* We want to disarm the buffers in these cases.
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*/
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static void sdma_hw_start_up(struct qib_pportdata *ppd)
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{
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struct qib_sdma_state *ss = &ppd->sdma_state;
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unsigned bufno;
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for (bufno = ss->first_sendbuf; bufno < ss->last_sendbuf; ++bufno)
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ppd->dd->f_sendctrl(ppd, QIB_SENDCTRL_DISARM_BUF(bufno));
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ppd->dd->f_sdma_hw_start_up(ppd);
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}
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static void sdma_sw_tear_down(struct qib_pportdata *ppd)
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{
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struct qib_sdma_state *ss = &ppd->sdma_state;
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/* Releasing this reference means the state machine has stopped. */
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sdma_put(ss);
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}
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static void sdma_start_sw_clean_up(struct qib_pportdata *ppd)
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{
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tasklet_hi_schedule(&ppd->sdma_sw_clean_up_task);
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}
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static void sdma_set_state(struct qib_pportdata *ppd,
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enum qib_sdma_states next_state)
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{
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struct qib_sdma_state *ss = &ppd->sdma_state;
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struct sdma_set_state_action *action = ss->set_state_action;
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unsigned op = 0;
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/* debugging bookkeeping */
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ss->previous_state = ss->current_state;
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ss->previous_op = ss->current_op;
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ss->current_state = next_state;
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if (action[next_state].op_enable)
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op |= QIB_SDMA_SENDCTRL_OP_ENABLE;
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if (action[next_state].op_intenable)
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op |= QIB_SDMA_SENDCTRL_OP_INTENABLE;
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if (action[next_state].op_halt)
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op |= QIB_SDMA_SENDCTRL_OP_HALT;
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if (action[next_state].op_drain)
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op |= QIB_SDMA_SENDCTRL_OP_DRAIN;
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if (action[next_state].go_s99_running_tofalse)
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ss->go_s99_running = 0;
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if (action[next_state].go_s99_running_totrue)
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ss->go_s99_running = 1;
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ss->current_op = op;
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ppd->dd->f_sdma_sendctrl(ppd, ss->current_op);
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}
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static void unmap_desc(struct qib_pportdata *ppd, unsigned head)
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{
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__le64 *descqp = &ppd->sdma_descq[head].qw[0];
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u64 desc[2];
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dma_addr_t addr;
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size_t len;
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desc[0] = le64_to_cpu(descqp[0]);
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desc[1] = le64_to_cpu(descqp[1]);
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addr = (desc[1] << 32) | (desc[0] >> 32);
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len = (desc[0] >> 14) & (0x7ffULL << 2);
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dma_unmap_single(&ppd->dd->pcidev->dev, addr, len, DMA_TO_DEVICE);
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}
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static int alloc_sdma(struct qib_pportdata *ppd)
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{
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ppd->sdma_descq_cnt = sdma_descq_cnt;
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if (!ppd->sdma_descq_cnt)
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ppd->sdma_descq_cnt = 256;
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/* Allocate memory for SendDMA descriptor FIFO */
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ppd->sdma_descq = dma_alloc_coherent(&ppd->dd->pcidev->dev,
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ppd->sdma_descq_cnt * sizeof(u64[2]), &ppd->sdma_descq_phys,
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GFP_KERNEL);
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if (!ppd->sdma_descq) {
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qib_dev_err(ppd->dd,
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"failed to allocate SendDMA descriptor FIFO memory\n");
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goto bail;
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}
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/* Allocate memory for DMA of head register to memory */
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ppd->sdma_head_dma = dma_alloc_coherent(&ppd->dd->pcidev->dev,
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PAGE_SIZE, &ppd->sdma_head_phys, GFP_KERNEL);
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if (!ppd->sdma_head_dma) {
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qib_dev_err(ppd->dd,
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"failed to allocate SendDMA head memory\n");
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goto cleanup_descq;
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}
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ppd->sdma_head_dma[0] = 0;
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return 0;
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cleanup_descq:
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dma_free_coherent(&ppd->dd->pcidev->dev,
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ppd->sdma_descq_cnt * sizeof(u64[2]), (void *)ppd->sdma_descq,
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ppd->sdma_descq_phys);
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ppd->sdma_descq = NULL;
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ppd->sdma_descq_phys = 0;
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bail:
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ppd->sdma_descq_cnt = 0;
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return -ENOMEM;
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}
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static void free_sdma(struct qib_pportdata *ppd)
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{
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struct qib_devdata *dd = ppd->dd;
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if (ppd->sdma_head_dma) {
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dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
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(void *)ppd->sdma_head_dma,
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ppd->sdma_head_phys);
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ppd->sdma_head_dma = NULL;
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ppd->sdma_head_phys = 0;
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}
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if (ppd->sdma_descq) {
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dma_free_coherent(&dd->pcidev->dev,
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ppd->sdma_descq_cnt * sizeof(u64[2]),
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ppd->sdma_descq, ppd->sdma_descq_phys);
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ppd->sdma_descq = NULL;
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ppd->sdma_descq_phys = 0;
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}
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}
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static inline void make_sdma_desc(struct qib_pportdata *ppd,
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u64 *sdmadesc, u64 addr, u64 dwlen,
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u64 dwoffset)
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{
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WARN_ON(addr & 3);
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/* SDmaPhyAddr[47:32] */
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sdmadesc[1] = addr >> 32;
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/* SDmaPhyAddr[31:0] */
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sdmadesc[0] = (addr & 0xfffffffcULL) << 32;
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/* SDmaGeneration[1:0] */
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sdmadesc[0] |= (ppd->sdma_generation & 3ULL) <<
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SDMA_DESC_GEN_LSB;
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/* SDmaDwordCount[10:0] */
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sdmadesc[0] |= (dwlen & 0x7ffULL) << SDMA_DESC_COUNT_LSB;
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/* SDmaBufOffset[12:2] */
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sdmadesc[0] |= dwoffset & 0x7ffULL;
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}
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/* sdma_lock must be held */
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int qib_sdma_make_progress(struct qib_pportdata *ppd)
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{
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struct list_head *lp = NULL;
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struct qib_sdma_txreq *txp = NULL;
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struct qib_devdata *dd = ppd->dd;
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int progress = 0;
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u16 hwhead;
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u16 idx = 0;
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hwhead = dd->f_sdma_gethead(ppd);
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/* The reason for some of the complexity of this code is that
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* not all descriptors have corresponding txps. So, we have to
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* be able to skip over descs until we wander into the range of
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* the next txp on the list.
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*/
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if (!list_empty(&ppd->sdma_activelist)) {
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lp = ppd->sdma_activelist.next;
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txp = list_entry(lp, struct qib_sdma_txreq, list);
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idx = txp->start_idx;
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}
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while (ppd->sdma_descq_head != hwhead) {
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/* if desc is part of this txp, unmap if needed */
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if (txp && (txp->flags & QIB_SDMA_TXREQ_F_FREEDESC) &&
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(idx == ppd->sdma_descq_head)) {
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unmap_desc(ppd, ppd->sdma_descq_head);
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if (++idx == ppd->sdma_descq_cnt)
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idx = 0;
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}
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/* increment dequed desc count */
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ppd->sdma_descq_removed++;
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/* advance head, wrap if needed */
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if (++ppd->sdma_descq_head == ppd->sdma_descq_cnt)
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ppd->sdma_descq_head = 0;
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/* if now past this txp's descs, do the callback */
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if (txp && txp->next_descq_idx == ppd->sdma_descq_head) {
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/* remove from active list */
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list_del_init(&txp->list);
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if (txp->callback)
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(*txp->callback)(txp, QIB_SDMA_TXREQ_S_OK);
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/* see if there is another txp */
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if (list_empty(&ppd->sdma_activelist))
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txp = NULL;
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else {
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lp = ppd->sdma_activelist.next;
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txp = list_entry(lp, struct qib_sdma_txreq,
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list);
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idx = txp->start_idx;
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}
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}
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progress = 1;
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}
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if (progress)
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qib_verbs_sdma_desc_avail(ppd, qib_sdma_descq_freecnt(ppd));
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return progress;
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}
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/*
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* This is called from interrupt context.
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*/
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void qib_sdma_intr(struct qib_pportdata *ppd)
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{
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unsigned long flags;
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spin_lock_irqsave(&ppd->sdma_lock, flags);
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__qib_sdma_intr(ppd);
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spin_unlock_irqrestore(&ppd->sdma_lock, flags);
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}
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void __qib_sdma_intr(struct qib_pportdata *ppd)
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{
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if (__qib_sdma_running(ppd)) {
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qib_sdma_make_progress(ppd);
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if (!list_empty(&ppd->sdma_userpending))
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qib_user_sdma_send_desc(ppd, &ppd->sdma_userpending);
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}
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}
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int qib_setup_sdma(struct qib_pportdata *ppd)
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{
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struct qib_devdata *dd = ppd->dd;
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unsigned long flags;
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int ret = 0;
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ret = alloc_sdma(ppd);
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if (ret)
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goto bail;
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/* set consistent sdma state */
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ppd->dd->f_sdma_init_early(ppd);
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spin_lock_irqsave(&ppd->sdma_lock, flags);
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sdma_set_state(ppd, qib_sdma_state_s00_hw_down);
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spin_unlock_irqrestore(&ppd->sdma_lock, flags);
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/* set up reference counting */
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kref_init(&ppd->sdma_state.kref);
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init_completion(&ppd->sdma_state.comp);
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ppd->sdma_generation = 0;
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ppd->sdma_descq_head = 0;
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ppd->sdma_descq_removed = 0;
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ppd->sdma_descq_added = 0;
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ppd->sdma_intrequest = 0;
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INIT_LIST_HEAD(&ppd->sdma_userpending);
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INIT_LIST_HEAD(&ppd->sdma_activelist);
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tasklet_setup(&ppd->sdma_sw_clean_up_task, sdma_sw_clean_up_task);
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ret = dd->f_init_sdma_regs(ppd);
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if (ret)
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goto bail_alloc;
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qib_sdma_process_event(ppd, qib_sdma_event_e10_go_hw_start);
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return 0;
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bail_alloc:
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qib_teardown_sdma(ppd);
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bail:
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return ret;
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}
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void qib_teardown_sdma(struct qib_pportdata *ppd)
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{
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qib_sdma_process_event(ppd, qib_sdma_event_e00_go_hw_down);
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/*
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* This waits for the state machine to exit so it is not
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* necessary to kill the sdma_sw_clean_up_task to make sure
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* it is not running.
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*/
|
|
sdma_finalput(&ppd->sdma_state);
|
|
|
|
free_sdma(ppd);
|
|
}
|
|
|
|
int qib_sdma_running(struct qib_pportdata *ppd)
|
|
{
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
spin_lock_irqsave(&ppd->sdma_lock, flags);
|
|
ret = __qib_sdma_running(ppd);
|
|
spin_unlock_irqrestore(&ppd->sdma_lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Complete a request when sdma not running; likely only request
|
|
* but to simplify the code, always queue it, then process the full
|
|
* activelist. We process the entire list to ensure that this particular
|
|
* request does get it's callback, but in the correct order.
|
|
* Must be called with sdma_lock held
|
|
*/
|
|
static void complete_sdma_err_req(struct qib_pportdata *ppd,
|
|
struct qib_verbs_txreq *tx)
|
|
{
|
|
struct qib_qp_priv *priv = tx->qp->priv;
|
|
|
|
atomic_inc(&priv->s_dma_busy);
|
|
/* no sdma descriptors, so no unmap_desc */
|
|
tx->txreq.start_idx = 0;
|
|
tx->txreq.next_descq_idx = 0;
|
|
list_add_tail(&tx->txreq.list, &ppd->sdma_activelist);
|
|
clear_sdma_activelist(ppd);
|
|
}
|
|
|
|
/*
|
|
* This function queues one IB packet onto the send DMA queue per call.
|
|
* The caller is responsible for checking:
|
|
* 1) The number of send DMA descriptor entries is less than the size of
|
|
* the descriptor queue.
|
|
* 2) The IB SGE addresses and lengths are 32-bit aligned
|
|
* (except possibly the last SGE's length)
|
|
* 3) The SGE addresses are suitable for passing to dma_map_single().
|
|
*/
|
|
int qib_sdma_verbs_send(struct qib_pportdata *ppd,
|
|
struct rvt_sge_state *ss, u32 dwords,
|
|
struct qib_verbs_txreq *tx)
|
|
{
|
|
unsigned long flags;
|
|
struct rvt_sge *sge;
|
|
struct rvt_qp *qp;
|
|
int ret = 0;
|
|
u16 tail;
|
|
__le64 *descqp;
|
|
u64 sdmadesc[2];
|
|
u32 dwoffset;
|
|
dma_addr_t addr;
|
|
struct qib_qp_priv *priv;
|
|
|
|
spin_lock_irqsave(&ppd->sdma_lock, flags);
|
|
|
|
retry:
|
|
if (unlikely(!__qib_sdma_running(ppd))) {
|
|
complete_sdma_err_req(ppd, tx);
|
|
goto unlock;
|
|
}
|
|
|
|
if (tx->txreq.sg_count > qib_sdma_descq_freecnt(ppd)) {
|
|
if (qib_sdma_make_progress(ppd))
|
|
goto retry;
|
|
if (ppd->dd->flags & QIB_HAS_SDMA_TIMEOUT)
|
|
ppd->dd->f_sdma_set_desc_cnt(ppd,
|
|
ppd->sdma_descq_cnt / 2);
|
|
goto busy;
|
|
}
|
|
|
|
dwoffset = tx->hdr_dwords;
|
|
make_sdma_desc(ppd, sdmadesc, (u64) tx->txreq.addr, dwoffset, 0);
|
|
|
|
sdmadesc[0] |= SDMA_DESC_FIRST;
|
|
if (tx->txreq.flags & QIB_SDMA_TXREQ_F_USELARGEBUF)
|
|
sdmadesc[0] |= SDMA_DESC_USE_LARGE_BUF;
|
|
|
|
/* write to the descq */
|
|
tail = ppd->sdma_descq_tail;
|
|
descqp = &ppd->sdma_descq[tail].qw[0];
|
|
*descqp++ = cpu_to_le64(sdmadesc[0]);
|
|
*descqp++ = cpu_to_le64(sdmadesc[1]);
|
|
|
|
/* increment the tail */
|
|
if (++tail == ppd->sdma_descq_cnt) {
|
|
tail = 0;
|
|
descqp = &ppd->sdma_descq[0].qw[0];
|
|
++ppd->sdma_generation;
|
|
}
|
|
|
|
tx->txreq.start_idx = tail;
|
|
|
|
sge = &ss->sge;
|
|
while (dwords) {
|
|
u32 dw;
|
|
u32 len = rvt_get_sge_length(sge, dwords << 2);
|
|
|
|
dw = (len + 3) >> 2;
|
|
addr = dma_map_single(&ppd->dd->pcidev->dev, sge->vaddr,
|
|
dw << 2, DMA_TO_DEVICE);
|
|
if (dma_mapping_error(&ppd->dd->pcidev->dev, addr)) {
|
|
ret = -ENOMEM;
|
|
goto unmap;
|
|
}
|
|
sdmadesc[0] = 0;
|
|
make_sdma_desc(ppd, sdmadesc, (u64) addr, dw, dwoffset);
|
|
/* SDmaUseLargeBuf has to be set in every descriptor */
|
|
if (tx->txreq.flags & QIB_SDMA_TXREQ_F_USELARGEBUF)
|
|
sdmadesc[0] |= SDMA_DESC_USE_LARGE_BUF;
|
|
/* write to the descq */
|
|
*descqp++ = cpu_to_le64(sdmadesc[0]);
|
|
*descqp++ = cpu_to_le64(sdmadesc[1]);
|
|
|
|
/* increment the tail */
|
|
if (++tail == ppd->sdma_descq_cnt) {
|
|
tail = 0;
|
|
descqp = &ppd->sdma_descq[0].qw[0];
|
|
++ppd->sdma_generation;
|
|
}
|
|
rvt_update_sge(ss, len, false);
|
|
dwoffset += dw;
|
|
dwords -= dw;
|
|
}
|
|
|
|
if (!tail)
|
|
descqp = &ppd->sdma_descq[ppd->sdma_descq_cnt].qw[0];
|
|
descqp -= 2;
|
|
descqp[0] |= cpu_to_le64(SDMA_DESC_LAST);
|
|
if (tx->txreq.flags & QIB_SDMA_TXREQ_F_HEADTOHOST)
|
|
descqp[0] |= cpu_to_le64(SDMA_DESC_DMA_HEAD);
|
|
if (tx->txreq.flags & QIB_SDMA_TXREQ_F_INTREQ)
|
|
descqp[0] |= cpu_to_le64(SDMA_DESC_INTR);
|
|
priv = tx->qp->priv;
|
|
atomic_inc(&priv->s_dma_busy);
|
|
tx->txreq.next_descq_idx = tail;
|
|
ppd->dd->f_sdma_update_tail(ppd, tail);
|
|
ppd->sdma_descq_added += tx->txreq.sg_count;
|
|
list_add_tail(&tx->txreq.list, &ppd->sdma_activelist);
|
|
goto unlock;
|
|
|
|
unmap:
|
|
for (;;) {
|
|
if (!tail)
|
|
tail = ppd->sdma_descq_cnt - 1;
|
|
else
|
|
tail--;
|
|
if (tail == ppd->sdma_descq_tail)
|
|
break;
|
|
unmap_desc(ppd, tail);
|
|
}
|
|
qp = tx->qp;
|
|
priv = qp->priv;
|
|
qib_put_txreq(tx);
|
|
spin_lock(&qp->r_lock);
|
|
spin_lock(&qp->s_lock);
|
|
if (qp->ibqp.qp_type == IB_QPT_RC) {
|
|
/* XXX what about error sending RDMA read responses? */
|
|
if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK)
|
|
rvt_error_qp(qp, IB_WC_GENERAL_ERR);
|
|
} else if (qp->s_wqe)
|
|
rvt_send_complete(qp, qp->s_wqe, IB_WC_GENERAL_ERR);
|
|
spin_unlock(&qp->s_lock);
|
|
spin_unlock(&qp->r_lock);
|
|
/* return zero to process the next send work request */
|
|
goto unlock;
|
|
|
|
busy:
|
|
qp = tx->qp;
|
|
priv = qp->priv;
|
|
spin_lock(&qp->s_lock);
|
|
if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
|
|
struct qib_ibdev *dev;
|
|
|
|
/*
|
|
* If we couldn't queue the DMA request, save the info
|
|
* and try again later rather than destroying the
|
|
* buffer and undoing the side effects of the copy.
|
|
*/
|
|
tx->ss = ss;
|
|
tx->dwords = dwords;
|
|
priv->s_tx = tx;
|
|
dev = &ppd->dd->verbs_dev;
|
|
spin_lock(&dev->rdi.pending_lock);
|
|
if (list_empty(&priv->iowait)) {
|
|
struct qib_ibport *ibp;
|
|
|
|
ibp = &ppd->ibport_data;
|
|
ibp->rvp.n_dmawait++;
|
|
qp->s_flags |= RVT_S_WAIT_DMA_DESC;
|
|
list_add_tail(&priv->iowait, &dev->dmawait);
|
|
}
|
|
spin_unlock(&dev->rdi.pending_lock);
|
|
qp->s_flags &= ~RVT_S_BUSY;
|
|
spin_unlock(&qp->s_lock);
|
|
ret = -EBUSY;
|
|
} else {
|
|
spin_unlock(&qp->s_lock);
|
|
qib_put_txreq(tx);
|
|
}
|
|
unlock:
|
|
spin_unlock_irqrestore(&ppd->sdma_lock, flags);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* sdma_lock should be acquired before calling this routine
|
|
*/
|
|
void dump_sdma_state(struct qib_pportdata *ppd)
|
|
{
|
|
struct qib_sdma_desc *descq;
|
|
struct qib_sdma_txreq *txp, *txpnext;
|
|
__le64 *descqp;
|
|
u64 desc[2];
|
|
u64 addr;
|
|
u16 gen, dwlen, dwoffset;
|
|
u16 head, tail, cnt;
|
|
|
|
head = ppd->sdma_descq_head;
|
|
tail = ppd->sdma_descq_tail;
|
|
cnt = qib_sdma_descq_freecnt(ppd);
|
|
descq = ppd->sdma_descq;
|
|
|
|
qib_dev_porterr(ppd->dd, ppd->port,
|
|
"SDMA ppd->sdma_descq_head: %u\n", head);
|
|
qib_dev_porterr(ppd->dd, ppd->port,
|
|
"SDMA ppd->sdma_descq_tail: %u\n", tail);
|
|
qib_dev_porterr(ppd->dd, ppd->port,
|
|
"SDMA sdma_descq_freecnt: %u\n", cnt);
|
|
|
|
/* print info for each entry in the descriptor queue */
|
|
while (head != tail) {
|
|
char flags[6] = { 'x', 'x', 'x', 'x', 'x', 0 };
|
|
|
|
descqp = &descq[head].qw[0];
|
|
desc[0] = le64_to_cpu(descqp[0]);
|
|
desc[1] = le64_to_cpu(descqp[1]);
|
|
flags[0] = (desc[0] & 1<<15) ? 'I' : '-';
|
|
flags[1] = (desc[0] & 1<<14) ? 'L' : 'S';
|
|
flags[2] = (desc[0] & 1<<13) ? 'H' : '-';
|
|
flags[3] = (desc[0] & 1<<12) ? 'F' : '-';
|
|
flags[4] = (desc[0] & 1<<11) ? 'L' : '-';
|
|
addr = (desc[1] << 32) | ((desc[0] >> 32) & 0xfffffffcULL);
|
|
gen = (desc[0] >> 30) & 3ULL;
|
|
dwlen = (desc[0] >> 14) & (0x7ffULL << 2);
|
|
dwoffset = (desc[0] & 0x7ffULL) << 2;
|
|
qib_dev_porterr(ppd->dd, ppd->port,
|
|
"SDMA sdmadesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes offset:%u bytes\n",
|
|
head, flags, addr, gen, dwlen, dwoffset);
|
|
if (++head == ppd->sdma_descq_cnt)
|
|
head = 0;
|
|
}
|
|
|
|
/* print dma descriptor indices from the TX requests */
|
|
list_for_each_entry_safe(txp, txpnext, &ppd->sdma_activelist,
|
|
list)
|
|
qib_dev_porterr(ppd->dd, ppd->port,
|
|
"SDMA txp->start_idx: %u txp->next_descq_idx: %u\n",
|
|
txp->start_idx, txp->next_descq_idx);
|
|
}
|
|
|
|
void qib_sdma_process_event(struct qib_pportdata *ppd,
|
|
enum qib_sdma_events event)
|
|
{
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&ppd->sdma_lock, flags);
|
|
|
|
__qib_sdma_process_event(ppd, event);
|
|
|
|
if (ppd->sdma_state.current_state == qib_sdma_state_s99_running)
|
|
qib_verbs_sdma_desc_avail(ppd, qib_sdma_descq_freecnt(ppd));
|
|
|
|
spin_unlock_irqrestore(&ppd->sdma_lock, flags);
|
|
}
|
|
|
|
void __qib_sdma_process_event(struct qib_pportdata *ppd,
|
|
enum qib_sdma_events event)
|
|
{
|
|
struct qib_sdma_state *ss = &ppd->sdma_state;
|
|
|
|
switch (ss->current_state) {
|
|
case qib_sdma_state_s00_hw_down:
|
|
switch (event) {
|
|
case qib_sdma_event_e00_go_hw_down:
|
|
break;
|
|
case qib_sdma_event_e30_go_running:
|
|
/*
|
|
* If down, but running requested (usually result
|
|
* of link up, then we need to start up.
|
|
* This can happen when hw down is requested while
|
|
* bringing the link up with traffic active on
|
|
* 7220, e.g. */
|
|
ss->go_s99_running = 1;
|
|
fallthrough; /* and start dma engine */
|
|
case qib_sdma_event_e10_go_hw_start:
|
|
/* This reference means the state machine is started */
|
|
sdma_get(&ppd->sdma_state);
|
|
sdma_set_state(ppd,
|
|
qib_sdma_state_s10_hw_start_up_wait);
|
|
break;
|
|
case qib_sdma_event_e20_hw_started:
|
|
break;
|
|
case qib_sdma_event_e40_sw_cleaned:
|
|
sdma_sw_tear_down(ppd);
|
|
break;
|
|
case qib_sdma_event_e50_hw_cleaned:
|
|
break;
|
|
case qib_sdma_event_e60_hw_halted:
|
|
break;
|
|
case qib_sdma_event_e70_go_idle:
|
|
break;
|
|
case qib_sdma_event_e7220_err_halted:
|
|
break;
|
|
case qib_sdma_event_e7322_err_halted:
|
|
break;
|
|
case qib_sdma_event_e90_timer_tick:
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case qib_sdma_state_s10_hw_start_up_wait:
|
|
switch (event) {
|
|
case qib_sdma_event_e00_go_hw_down:
|
|
sdma_set_state(ppd, qib_sdma_state_s00_hw_down);
|
|
sdma_sw_tear_down(ppd);
|
|
break;
|
|
case qib_sdma_event_e10_go_hw_start:
|
|
break;
|
|
case qib_sdma_event_e20_hw_started:
|
|
sdma_set_state(ppd, ss->go_s99_running ?
|
|
qib_sdma_state_s99_running :
|
|
qib_sdma_state_s20_idle);
|
|
break;
|
|
case qib_sdma_event_e30_go_running:
|
|
ss->go_s99_running = 1;
|
|
break;
|
|
case qib_sdma_event_e40_sw_cleaned:
|
|
break;
|
|
case qib_sdma_event_e50_hw_cleaned:
|
|
break;
|
|
case qib_sdma_event_e60_hw_halted:
|
|
break;
|
|
case qib_sdma_event_e70_go_idle:
|
|
ss->go_s99_running = 0;
|
|
break;
|
|
case qib_sdma_event_e7220_err_halted:
|
|
break;
|
|
case qib_sdma_event_e7322_err_halted:
|
|
break;
|
|
case qib_sdma_event_e90_timer_tick:
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case qib_sdma_state_s20_idle:
|
|
switch (event) {
|
|
case qib_sdma_event_e00_go_hw_down:
|
|
sdma_set_state(ppd, qib_sdma_state_s00_hw_down);
|
|
sdma_sw_tear_down(ppd);
|
|
break;
|
|
case qib_sdma_event_e10_go_hw_start:
|
|
break;
|
|
case qib_sdma_event_e20_hw_started:
|
|
break;
|
|
case qib_sdma_event_e30_go_running:
|
|
sdma_set_state(ppd, qib_sdma_state_s99_running);
|
|
ss->go_s99_running = 1;
|
|
break;
|
|
case qib_sdma_event_e40_sw_cleaned:
|
|
break;
|
|
case qib_sdma_event_e50_hw_cleaned:
|
|
break;
|
|
case qib_sdma_event_e60_hw_halted:
|
|
break;
|
|
case qib_sdma_event_e70_go_idle:
|
|
break;
|
|
case qib_sdma_event_e7220_err_halted:
|
|
break;
|
|
case qib_sdma_event_e7322_err_halted:
|
|
break;
|
|
case qib_sdma_event_e90_timer_tick:
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case qib_sdma_state_s30_sw_clean_up_wait:
|
|
switch (event) {
|
|
case qib_sdma_event_e00_go_hw_down:
|
|
sdma_set_state(ppd, qib_sdma_state_s00_hw_down);
|
|
break;
|
|
case qib_sdma_event_e10_go_hw_start:
|
|
break;
|
|
case qib_sdma_event_e20_hw_started:
|
|
break;
|
|
case qib_sdma_event_e30_go_running:
|
|
ss->go_s99_running = 1;
|
|
break;
|
|
case qib_sdma_event_e40_sw_cleaned:
|
|
sdma_set_state(ppd,
|
|
qib_sdma_state_s10_hw_start_up_wait);
|
|
sdma_hw_start_up(ppd);
|
|
break;
|
|
case qib_sdma_event_e50_hw_cleaned:
|
|
break;
|
|
case qib_sdma_event_e60_hw_halted:
|
|
break;
|
|
case qib_sdma_event_e70_go_idle:
|
|
ss->go_s99_running = 0;
|
|
break;
|
|
case qib_sdma_event_e7220_err_halted:
|
|
break;
|
|
case qib_sdma_event_e7322_err_halted:
|
|
break;
|
|
case qib_sdma_event_e90_timer_tick:
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case qib_sdma_state_s40_hw_clean_up_wait:
|
|
switch (event) {
|
|
case qib_sdma_event_e00_go_hw_down:
|
|
sdma_set_state(ppd, qib_sdma_state_s00_hw_down);
|
|
sdma_start_sw_clean_up(ppd);
|
|
break;
|
|
case qib_sdma_event_e10_go_hw_start:
|
|
break;
|
|
case qib_sdma_event_e20_hw_started:
|
|
break;
|
|
case qib_sdma_event_e30_go_running:
|
|
ss->go_s99_running = 1;
|
|
break;
|
|
case qib_sdma_event_e40_sw_cleaned:
|
|
break;
|
|
case qib_sdma_event_e50_hw_cleaned:
|
|
sdma_set_state(ppd,
|
|
qib_sdma_state_s30_sw_clean_up_wait);
|
|
sdma_start_sw_clean_up(ppd);
|
|
break;
|
|
case qib_sdma_event_e60_hw_halted:
|
|
break;
|
|
case qib_sdma_event_e70_go_idle:
|
|
ss->go_s99_running = 0;
|
|
break;
|
|
case qib_sdma_event_e7220_err_halted:
|
|
break;
|
|
case qib_sdma_event_e7322_err_halted:
|
|
break;
|
|
case qib_sdma_event_e90_timer_tick:
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case qib_sdma_state_s50_hw_halt_wait:
|
|
switch (event) {
|
|
case qib_sdma_event_e00_go_hw_down:
|
|
sdma_set_state(ppd, qib_sdma_state_s00_hw_down);
|
|
sdma_start_sw_clean_up(ppd);
|
|
break;
|
|
case qib_sdma_event_e10_go_hw_start:
|
|
break;
|
|
case qib_sdma_event_e20_hw_started:
|
|
break;
|
|
case qib_sdma_event_e30_go_running:
|
|
ss->go_s99_running = 1;
|
|
break;
|
|
case qib_sdma_event_e40_sw_cleaned:
|
|
break;
|
|
case qib_sdma_event_e50_hw_cleaned:
|
|
break;
|
|
case qib_sdma_event_e60_hw_halted:
|
|
sdma_set_state(ppd,
|
|
qib_sdma_state_s40_hw_clean_up_wait);
|
|
ppd->dd->f_sdma_hw_clean_up(ppd);
|
|
break;
|
|
case qib_sdma_event_e70_go_idle:
|
|
ss->go_s99_running = 0;
|
|
break;
|
|
case qib_sdma_event_e7220_err_halted:
|
|
break;
|
|
case qib_sdma_event_e7322_err_halted:
|
|
break;
|
|
case qib_sdma_event_e90_timer_tick:
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case qib_sdma_state_s99_running:
|
|
switch (event) {
|
|
case qib_sdma_event_e00_go_hw_down:
|
|
sdma_set_state(ppd, qib_sdma_state_s00_hw_down);
|
|
sdma_start_sw_clean_up(ppd);
|
|
break;
|
|
case qib_sdma_event_e10_go_hw_start:
|
|
break;
|
|
case qib_sdma_event_e20_hw_started:
|
|
break;
|
|
case qib_sdma_event_e30_go_running:
|
|
break;
|
|
case qib_sdma_event_e40_sw_cleaned:
|
|
break;
|
|
case qib_sdma_event_e50_hw_cleaned:
|
|
break;
|
|
case qib_sdma_event_e60_hw_halted:
|
|
sdma_set_state(ppd,
|
|
qib_sdma_state_s30_sw_clean_up_wait);
|
|
sdma_start_sw_clean_up(ppd);
|
|
break;
|
|
case qib_sdma_event_e70_go_idle:
|
|
sdma_set_state(ppd, qib_sdma_state_s50_hw_halt_wait);
|
|
ss->go_s99_running = 0;
|
|
break;
|
|
case qib_sdma_event_e7220_err_halted:
|
|
sdma_set_state(ppd,
|
|
qib_sdma_state_s30_sw_clean_up_wait);
|
|
sdma_start_sw_clean_up(ppd);
|
|
break;
|
|
case qib_sdma_event_e7322_err_halted:
|
|
sdma_set_state(ppd, qib_sdma_state_s50_hw_halt_wait);
|
|
break;
|
|
case qib_sdma_event_e90_timer_tick:
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
ss->last_event = event;
|
|
}
|