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-----BEGIN PGP SIGNATURE----- iQHJBAABCgAzFiEEi8GdvG6xMhdgpu/4sUSA/TofvsgFAmHi+xgVHHl1cnkubm9y b3ZAZ21haWwuY29tAAoJELFEgP06H77IxdoMAMf3E+L51Ys/4iAiyJQNVoT3aIBC A8ZVOB9he1OA3o3wBNIRKmICHk+ovnfCWcXTr9fG/Ade2wJz88NAsGPQ1Phywb+s iGlpySllFN72RT9ZqtJhLEzgoHHOL0CzTW07TN9GJy4gQA2h2G9CTP+OmsQdnVqE m9Fn3PSlJ5lhzePlKfnln8rGZFgrriJakfEFPC79n/7an4+2Hvkb5rWigo7KQc4Z 9YNqYUcHWZFUgq80adxEb9LlbMXdD+Z/8fCjOrAatuwVkD4RDt6iKD0mFGjHXGL7 MZ9KRS8AfZXawmetk3jjtsV+/QkeS+Deuu7k0FoO0Th2QV7BGSDhsLXAS5By/MOC nfSyHhnXHzCsBMyVNrJHmNhEZoN29+tRwI84JX9lWcf/OLANcCofnP6f2UIX7tZY CAZAgVELp+0YQXdybrfzTQ8BT3TinjS/aZtCrYijRendI1GwUXcyl69vdOKqAHuk 5jy8k/xHyp+ZWu6v+PyAAAEGowY++qhL0fmszA== =RKW4 -----END PGP SIGNATURE----- Merge tag 'bitmap-5.17-rc1' of git://github.com/norov/linux Pull bitmap updates from Yury Norov: - introduce for_each_set_bitrange() - use find_first_*_bit() instead of find_next_*_bit() where possible - unify for_each_bit() macros * tag 'bitmap-5.17-rc1' of git://github.com/norov/linux: vsprintf: rework bitmap_list_string lib: bitmap: add performance test for bitmap_print_to_pagebuf bitmap: unify find_bit operations mm/percpu: micro-optimize pcpu_is_populated() Replace for_each_*_bit_from() with for_each_*_bit() where appropriate find: micro-optimize for_each_{set,clear}_bit() include/linux: move for_each_bit() macros from bitops.h to find.h cpumask: replace cpumask_next_* with cpumask_first_* where appropriate tools: sync tools/bitmap with mother linux all: replace find_next{,_zero}_bit with find_first{,_zero}_bit where appropriate cpumask: use find_first_and_bit() lib: add find_first_and_bit() arch: remove GENERIC_FIND_FIRST_BIT entirely include: move find.h from asm_generic to linux bitops: move find_bit_*_le functions from le.h to find.h bitops: protect find_first_{,zero}_bit properly
962 lines
22 KiB
C
962 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
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*
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* Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
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*
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* Authors: Kishon Vijay Abraham I <kishon@ti.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/resource.h>
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#include <linux/types.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/gpio/consumer.h>
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#include "../../pci.h"
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#include "pcie-designware.h"
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/* PCIe controller wrapper DRA7XX configuration registers */
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#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
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#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
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#define ERR_SYS BIT(0)
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#define ERR_FATAL BIT(1)
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#define ERR_NONFATAL BIT(2)
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#define ERR_COR BIT(3)
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#define ERR_AXI BIT(4)
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#define ERR_ECRC BIT(5)
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#define PME_TURN_OFF BIT(8)
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#define PME_TO_ACK BIT(9)
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#define PM_PME BIT(10)
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#define LINK_REQ_RST BIT(11)
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#define LINK_UP_EVT BIT(12)
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#define CFG_BME_EVT BIT(13)
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#define CFG_MSE_EVT BIT(14)
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#define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
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ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
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LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
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#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
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#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
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#define INTA BIT(0)
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#define INTB BIT(1)
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#define INTC BIT(2)
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#define INTD BIT(3)
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#define MSI BIT(4)
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#define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
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#define PCIECTRL_TI_CONF_DEVICE_TYPE 0x0100
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#define DEVICE_TYPE_EP 0x0
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#define DEVICE_TYPE_LEG_EP 0x1
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#define DEVICE_TYPE_RC 0x4
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#define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
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#define LTSSM_EN 0x1
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#define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
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#define LINK_UP BIT(16)
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#define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
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#define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124
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#define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128
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#define PCIECTRL_TI_CONF_MSI_XMT 0x012c
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#define MSI_REQ_GRANT BIT(0)
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#define MSI_VECTOR_SHIFT 7
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#define PCIE_1LANE_2LANE_SELECTION BIT(13)
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#define PCIE_B1C0_MODE_SEL BIT(2)
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#define PCIE_B0_B1_TSYNCEN BIT(0)
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struct dra7xx_pcie {
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struct dw_pcie *pci;
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void __iomem *base; /* DT ti_conf */
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int phy_count; /* DT phy-names count */
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struct phy **phy;
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struct irq_domain *irq_domain;
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struct clk *clk;
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enum dw_pcie_device_mode mode;
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};
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struct dra7xx_pcie_of_data {
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enum dw_pcie_device_mode mode;
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u32 b1co_mode_sel_mask;
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};
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#define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
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static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
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{
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return readl(pcie->base + offset);
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}
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static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
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u32 value)
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{
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writel(value, pcie->base + offset);
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}
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static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
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{
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return pci_addr & DRA7XX_CPU_TO_BUS_ADDR;
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}
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static int dra7xx_pcie_link_up(struct dw_pcie *pci)
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{
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
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return !!(reg & LINK_UP);
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}
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static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
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{
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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u32 reg;
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reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
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reg &= ~LTSSM_EN;
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
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}
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static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
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{
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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struct device *dev = pci->dev;
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u32 reg;
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if (dw_pcie_link_up(pci)) {
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dev_err(dev, "link is already up\n");
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return 0;
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}
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reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
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reg |= LTSSM_EN;
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
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return 0;
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}
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static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
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{
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
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LEG_EP_INTERRUPTS | MSI);
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dra7xx_pcie_writel(dra7xx,
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PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
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MSI | LEG_EP_INTERRUPTS);
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}
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static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
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{
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
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INTERRUPTS);
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
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INTERRUPTS);
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}
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static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
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{
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dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
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dra7xx_pcie_enable_msi_interrupts(dra7xx);
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}
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static int dra7xx_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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dra7xx_pcie_enable_interrupts(dra7xx);
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return 0;
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}
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static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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}
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static const struct irq_domain_ops intx_domain_ops = {
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.map = dra7xx_pcie_intx_map,
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.xlate = pci_irqd_intx_xlate,
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};
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static int dra7xx_pcie_handle_msi(struct pcie_port *pp, int index)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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unsigned long val;
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int pos;
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val = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
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(index * MSI_REG_CTRL_BLOCK_SIZE));
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if (!val)
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return 0;
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pos = find_first_bit(&val, MAX_MSI_IRQS_PER_CTRL);
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while (pos != MAX_MSI_IRQS_PER_CTRL) {
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generic_handle_domain_irq(pp->irq_domain,
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(index * MAX_MSI_IRQS_PER_CTRL) + pos);
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pos++;
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pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, pos);
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}
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return 1;
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}
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static void dra7xx_pcie_handle_msi_irq(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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int ret, i, count, num_ctrls;
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num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
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/**
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* Need to make sure all MSI status bits read 0 before exiting.
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* Else, new MSI IRQs are not registered by the wrapper. Have an
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* upperbound for the loop and exit the IRQ in case of IRQ flood
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* to avoid locking up system in interrupt context.
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*/
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count = 0;
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do {
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ret = 0;
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for (i = 0; i < num_ctrls; i++)
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ret |= dra7xx_pcie_handle_msi(pp, i);
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count++;
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} while (ret && count <= 1000);
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if (count > 1000)
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dev_warn_ratelimited(pci->dev,
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"Too many MSI IRQs to handle\n");
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}
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static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct dra7xx_pcie *dra7xx;
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struct dw_pcie *pci;
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struct pcie_port *pp;
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unsigned long reg;
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u32 bit;
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chained_irq_enter(chip, desc);
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pp = irq_desc_get_handler_data(desc);
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pci = to_dw_pcie_from_pp(pp);
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dra7xx = to_dra7xx_pcie(pci);
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reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
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switch (reg) {
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case MSI:
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dra7xx_pcie_handle_msi_irq(pp);
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break;
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case INTA:
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case INTB:
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case INTC:
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case INTD:
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for_each_set_bit(bit, ®, PCI_NUM_INTX)
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generic_handle_domain_irq(dra7xx->irq_domain, bit);
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break;
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}
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chained_irq_exit(chip, desc);
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}
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static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
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{
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struct dra7xx_pcie *dra7xx = arg;
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struct dw_pcie *pci = dra7xx->pci;
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struct device *dev = pci->dev;
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struct dw_pcie_ep *ep = &pci->ep;
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u32 reg;
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reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
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if (reg & ERR_SYS)
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dev_dbg(dev, "System Error\n");
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if (reg & ERR_FATAL)
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dev_dbg(dev, "Fatal Error\n");
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if (reg & ERR_NONFATAL)
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dev_dbg(dev, "Non Fatal Error\n");
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if (reg & ERR_COR)
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dev_dbg(dev, "Correctable Error\n");
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if (reg & ERR_AXI)
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dev_dbg(dev, "AXI tag lookup fatal Error\n");
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if (reg & ERR_ECRC)
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dev_dbg(dev, "ECRC Error\n");
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if (reg & PME_TURN_OFF)
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dev_dbg(dev,
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"Power Management Event Turn-Off message received\n");
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if (reg & PME_TO_ACK)
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dev_dbg(dev,
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"Power Management Turn-Off Ack message received\n");
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if (reg & PM_PME)
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dev_dbg(dev, "PM Power Management Event message received\n");
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if (reg & LINK_REQ_RST)
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dev_dbg(dev, "Link Request Reset\n");
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if (reg & LINK_UP_EVT) {
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if (dra7xx->mode == DW_PCIE_EP_TYPE)
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dw_pcie_ep_linkup(ep);
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dev_dbg(dev, "Link-up state change\n");
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}
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if (reg & CFG_BME_EVT)
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dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
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if (reg & CFG_MSE_EVT)
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dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
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return IRQ_HANDLED;
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}
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static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct device *dev = pci->dev;
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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struct device_node *node = dev->of_node;
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struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
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if (!pcie_intc_node) {
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dev_err(dev, "No PCIe Intc node found\n");
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return -ENODEV;
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}
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irq_set_chained_handler_and_data(pp->irq, dra7xx_pcie_msi_irq_handler,
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pp);
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dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
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&intx_domain_ops, pp);
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of_node_put(pcie_intc_node);
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if (!dra7xx->irq_domain) {
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dev_err(dev, "Failed to get a INTx IRQ domain\n");
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return -ENODEV;
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}
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return 0;
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}
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static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
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.host_init = dra7xx_pcie_host_init,
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};
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static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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enum pci_barno bar;
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for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
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dw_pcie_ep_reset_bar(pci, bar);
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dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
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}
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static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx)
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{
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dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1);
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mdelay(1);
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dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1);
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}
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static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
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u8 interrupt_num)
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{
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u32 reg;
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reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT;
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reg |= MSI_REQ_GRANT;
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dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
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}
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static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
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enum pci_epc_irq_type type, u16 interrupt_num)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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switch (type) {
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case PCI_EPC_IRQ_LEGACY:
|
|
dra7xx_pcie_raise_legacy_irq(dra7xx);
|
|
break;
|
|
case PCI_EPC_IRQ_MSI:
|
|
dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
|
|
break;
|
|
default:
|
|
dev_err(pci->dev, "UNKNOWN IRQ type\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pci_epc_features dra7xx_pcie_epc_features = {
|
|
.linkup_notifier = true,
|
|
.msi_capable = true,
|
|
.msix_capable = false,
|
|
};
|
|
|
|
static const struct pci_epc_features*
|
|
dra7xx_pcie_get_features(struct dw_pcie_ep *ep)
|
|
{
|
|
return &dra7xx_pcie_epc_features;
|
|
}
|
|
|
|
static const struct dw_pcie_ep_ops pcie_ep_ops = {
|
|
.ep_init = dra7xx_pcie_ep_init,
|
|
.raise_irq = dra7xx_pcie_raise_irq,
|
|
.get_features = dra7xx_pcie_get_features,
|
|
};
|
|
|
|
static int dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
|
|
struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
struct dw_pcie_ep *ep;
|
|
struct device *dev = &pdev->dev;
|
|
struct dw_pcie *pci = dra7xx->pci;
|
|
|
|
ep = &pci->ep;
|
|
ep->ops = &pcie_ep_ops;
|
|
|
|
pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "ep_dbics");
|
|
if (IS_ERR(pci->dbi_base))
|
|
return PTR_ERR(pci->dbi_base);
|
|
|
|
pci->dbi_base2 =
|
|
devm_platform_ioremap_resource_byname(pdev, "ep_dbics2");
|
|
if (IS_ERR(pci->dbi_base2))
|
|
return PTR_ERR(pci->dbi_base2);
|
|
|
|
ret = dw_pcie_ep_init(ep);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize endpoint\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
|
|
struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
struct dw_pcie *pci = dra7xx->pci;
|
|
struct pcie_port *pp = &pci->pp;
|
|
struct device *dev = pci->dev;
|
|
|
|
pp->irq = platform_get_irq(pdev, 1);
|
|
if (pp->irq < 0)
|
|
return pp->irq;
|
|
|
|
/* MSI IRQ is muxed */
|
|
pp->msi_irq = -ENODEV;
|
|
|
|
ret = dra7xx_pcie_init_irq_domain(pp);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc_dbics");
|
|
if (IS_ERR(pci->dbi_base))
|
|
return PTR_ERR(pci->dbi_base);
|
|
|
|
pp->ops = &dra7xx_pcie_host_ops;
|
|
|
|
ret = dw_pcie_host_init(pp);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize host\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dw_pcie_ops dw_pcie_ops = {
|
|
.cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup,
|
|
.start_link = dra7xx_pcie_establish_link,
|
|
.stop_link = dra7xx_pcie_stop_link,
|
|
.link_up = dra7xx_pcie_link_up,
|
|
};
|
|
|
|
static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
|
|
{
|
|
int phy_count = dra7xx->phy_count;
|
|
|
|
while (phy_count--) {
|
|
phy_power_off(dra7xx->phy[phy_count]);
|
|
phy_exit(dra7xx->phy[phy_count]);
|
|
}
|
|
}
|
|
|
|
static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
|
|
{
|
|
int phy_count = dra7xx->phy_count;
|
|
int ret;
|
|
int i;
|
|
|
|
for (i = 0; i < phy_count; i++) {
|
|
ret = phy_set_mode(dra7xx->phy[i], PHY_MODE_PCIE);
|
|
if (ret < 0)
|
|
goto err_phy;
|
|
|
|
ret = phy_init(dra7xx->phy[i]);
|
|
if (ret < 0)
|
|
goto err_phy;
|
|
|
|
ret = phy_power_on(dra7xx->phy[i]);
|
|
if (ret < 0) {
|
|
phy_exit(dra7xx->phy[i]);
|
|
goto err_phy;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_phy:
|
|
while (--i >= 0) {
|
|
phy_power_off(dra7xx->phy[i]);
|
|
phy_exit(dra7xx->phy[i]);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = {
|
|
.mode = DW_PCIE_RC_TYPE,
|
|
};
|
|
|
|
static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
|
|
.mode = DW_PCIE_EP_TYPE,
|
|
};
|
|
|
|
static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = {
|
|
.b1co_mode_sel_mask = BIT(2),
|
|
.mode = DW_PCIE_RC_TYPE,
|
|
};
|
|
|
|
static const struct dra7xx_pcie_of_data dra726_pcie_rc_of_data = {
|
|
.b1co_mode_sel_mask = GENMASK(3, 2),
|
|
.mode = DW_PCIE_RC_TYPE,
|
|
};
|
|
|
|
static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = {
|
|
.b1co_mode_sel_mask = BIT(2),
|
|
.mode = DW_PCIE_EP_TYPE,
|
|
};
|
|
|
|
static const struct dra7xx_pcie_of_data dra726_pcie_ep_of_data = {
|
|
.b1co_mode_sel_mask = GENMASK(3, 2),
|
|
.mode = DW_PCIE_EP_TYPE,
|
|
};
|
|
|
|
static const struct of_device_id of_dra7xx_pcie_match[] = {
|
|
{
|
|
.compatible = "ti,dra7-pcie",
|
|
.data = &dra7xx_pcie_rc_of_data,
|
|
},
|
|
{
|
|
.compatible = "ti,dra7-pcie-ep",
|
|
.data = &dra7xx_pcie_ep_of_data,
|
|
},
|
|
{
|
|
.compatible = "ti,dra746-pcie-rc",
|
|
.data = &dra746_pcie_rc_of_data,
|
|
},
|
|
{
|
|
.compatible = "ti,dra726-pcie-rc",
|
|
.data = &dra726_pcie_rc_of_data,
|
|
},
|
|
{
|
|
.compatible = "ti,dra746-pcie-ep",
|
|
.data = &dra746_pcie_ep_of_data,
|
|
},
|
|
{
|
|
.compatible = "ti,dra726-pcie-ep",
|
|
.data = &dra726_pcie_ep_of_data,
|
|
},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, of_dra7xx_pcie_match);
|
|
|
|
/*
|
|
* dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
|
|
* @dra7xx: the dra7xx device where the workaround should be applied
|
|
*
|
|
* Access to the PCIe slave port that are not 32-bit aligned will result
|
|
* in incorrect mapping to TLP Address and Byte enable fields. Therefore,
|
|
* byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
|
|
* 0x3.
|
|
*
|
|
* To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
|
|
*/
|
|
static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct device_node *np = dev->of_node;
|
|
struct of_phandle_args args;
|
|
struct regmap *regmap;
|
|
|
|
regmap = syscon_regmap_lookup_by_phandle(np,
|
|
"ti,syscon-unaligned-access");
|
|
if (IS_ERR(regmap)) {
|
|
dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access",
|
|
2, 0, &args);
|
|
if (ret) {
|
|
dev_err(dev, "failed to parse ti,syscon-unaligned-access\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = regmap_update_bits(regmap, args.args[0], args.args[1],
|
|
args.args[1]);
|
|
if (ret)
|
|
dev_err(dev, "failed to enable unaligned access\n");
|
|
|
|
of_node_put(args.np);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dra7xx_pcie_configure_two_lane(struct device *dev,
|
|
u32 b1co_mode_sel_mask)
|
|
{
|
|
struct device_node *np = dev->of_node;
|
|
struct regmap *pcie_syscon;
|
|
unsigned int pcie_reg;
|
|
u32 mask;
|
|
u32 val;
|
|
|
|
pcie_syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-lane-sel");
|
|
if (IS_ERR(pcie_syscon)) {
|
|
dev_err(dev, "unable to get ti,syscon-lane-sel\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (of_property_read_u32_index(np, "ti,syscon-lane-sel", 1,
|
|
&pcie_reg)) {
|
|
dev_err(dev, "couldn't get lane selection reg offset\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
mask = b1co_mode_sel_mask | PCIE_B0_B1_TSYNCEN;
|
|
val = PCIE_B1C0_MODE_SEL | PCIE_B0_B1_TSYNCEN;
|
|
regmap_update_bits(pcie_syscon, pcie_reg, mask, val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dra7xx_pcie_probe(struct platform_device *pdev)
|
|
{
|
|
u32 reg;
|
|
int ret;
|
|
int irq;
|
|
int i;
|
|
int phy_count;
|
|
struct phy **phy;
|
|
struct device_link **link;
|
|
void __iomem *base;
|
|
struct dw_pcie *pci;
|
|
struct dra7xx_pcie *dra7xx;
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
char name[10];
|
|
struct gpio_desc *reset;
|
|
const struct dra7xx_pcie_of_data *data;
|
|
enum dw_pcie_device_mode mode;
|
|
u32 b1co_mode_sel_mask;
|
|
|
|
data = of_device_get_match_data(dev);
|
|
if (!data)
|
|
return -EINVAL;
|
|
|
|
mode = (enum dw_pcie_device_mode)data->mode;
|
|
b1co_mode_sel_mask = data->b1co_mode_sel_mask;
|
|
|
|
dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
|
|
if (!dra7xx)
|
|
return -ENOMEM;
|
|
|
|
pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
|
|
if (!pci)
|
|
return -ENOMEM;
|
|
|
|
pci->dev = dev;
|
|
pci->ops = &dw_pcie_ops;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
base = devm_platform_ioremap_resource_byname(pdev, "ti_conf");
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
phy_count = of_property_count_strings(np, "phy-names");
|
|
if (phy_count < 0) {
|
|
dev_err(dev, "unable to find the strings\n");
|
|
return phy_count;
|
|
}
|
|
|
|
phy = devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL);
|
|
if (!phy)
|
|
return -ENOMEM;
|
|
|
|
link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
|
|
if (!link)
|
|
return -ENOMEM;
|
|
|
|
dra7xx->clk = devm_clk_get_optional(dev, NULL);
|
|
if (IS_ERR(dra7xx->clk))
|
|
return dev_err_probe(dev, PTR_ERR(dra7xx->clk),
|
|
"clock request failed");
|
|
|
|
ret = clk_prepare_enable(dra7xx->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
for (i = 0; i < phy_count; i++) {
|
|
snprintf(name, sizeof(name), "pcie-phy%d", i);
|
|
phy[i] = devm_phy_get(dev, name);
|
|
if (IS_ERR(phy[i]))
|
|
return PTR_ERR(phy[i]);
|
|
|
|
link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
|
|
if (!link[i]) {
|
|
ret = -EINVAL;
|
|
goto err_link;
|
|
}
|
|
}
|
|
|
|
dra7xx->base = base;
|
|
dra7xx->phy = phy;
|
|
dra7xx->pci = pci;
|
|
dra7xx->phy_count = phy_count;
|
|
|
|
if (phy_count == 2) {
|
|
ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask);
|
|
if (ret < 0)
|
|
dra7xx->phy_count = 1; /* Fallback to x1 lane mode */
|
|
}
|
|
|
|
ret = dra7xx_pcie_enable_phy(dra7xx);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable phy\n");
|
|
return ret;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, dra7xx);
|
|
|
|
pm_runtime_enable(dev);
|
|
ret = pm_runtime_get_sync(dev);
|
|
if (ret < 0) {
|
|
dev_err(dev, "pm_runtime_get_sync failed\n");
|
|
goto err_get_sync;
|
|
}
|
|
|
|
reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
|
|
if (IS_ERR(reset)) {
|
|
ret = PTR_ERR(reset);
|
|
dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
|
|
goto err_gpio;
|
|
}
|
|
|
|
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
|
|
reg &= ~LTSSM_EN;
|
|
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
|
|
|
|
switch (mode) {
|
|
case DW_PCIE_RC_TYPE:
|
|
if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
|
|
ret = -ENODEV;
|
|
goto err_gpio;
|
|
}
|
|
|
|
dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
|
|
DEVICE_TYPE_RC);
|
|
|
|
ret = dra7xx_pcie_unaligned_memaccess(dev);
|
|
if (ret)
|
|
dev_err(dev, "WA for Errata i870 not applied\n");
|
|
|
|
ret = dra7xx_add_pcie_port(dra7xx, pdev);
|
|
if (ret < 0)
|
|
goto err_gpio;
|
|
break;
|
|
case DW_PCIE_EP_TYPE:
|
|
if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) {
|
|
ret = -ENODEV;
|
|
goto err_gpio;
|
|
}
|
|
|
|
dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
|
|
DEVICE_TYPE_EP);
|
|
|
|
ret = dra7xx_pcie_unaligned_memaccess(dev);
|
|
if (ret)
|
|
goto err_gpio;
|
|
|
|
ret = dra7xx_add_pcie_ep(dra7xx, pdev);
|
|
if (ret < 0)
|
|
goto err_gpio;
|
|
break;
|
|
default:
|
|
dev_err(dev, "INVALID device type %d\n", mode);
|
|
}
|
|
dra7xx->mode = mode;
|
|
|
|
ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
|
|
IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
|
|
if (ret) {
|
|
dev_err(dev, "failed to request irq\n");
|
|
goto err_gpio;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_gpio:
|
|
err_get_sync:
|
|
pm_runtime_put(dev);
|
|
pm_runtime_disable(dev);
|
|
dra7xx_pcie_disable_phy(dra7xx);
|
|
|
|
err_link:
|
|
while (--i >= 0)
|
|
device_link_del(link[i]);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int dra7xx_pcie_suspend(struct device *dev)
|
|
{
|
|
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
|
|
struct dw_pcie *pci = dra7xx->pci;
|
|
u32 val;
|
|
|
|
if (dra7xx->mode != DW_PCIE_RC_TYPE)
|
|
return 0;
|
|
|
|
/* clear MSE */
|
|
val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
|
|
val &= ~PCI_COMMAND_MEMORY;
|
|
dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dra7xx_pcie_resume(struct device *dev)
|
|
{
|
|
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
|
|
struct dw_pcie *pci = dra7xx->pci;
|
|
u32 val;
|
|
|
|
if (dra7xx->mode != DW_PCIE_RC_TYPE)
|
|
return 0;
|
|
|
|
/* set MSE */
|
|
val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
|
|
val |= PCI_COMMAND_MEMORY;
|
|
dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dra7xx_pcie_suspend_noirq(struct device *dev)
|
|
{
|
|
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
|
|
|
|
dra7xx_pcie_disable_phy(dra7xx);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dra7xx_pcie_resume_noirq(struct device *dev)
|
|
{
|
|
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = dra7xx_pcie_enable_phy(dra7xx);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable phy\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static void dra7xx_pcie_shutdown(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
dra7xx_pcie_stop_link(dra7xx->pci);
|
|
|
|
ret = pm_runtime_put_sync(dev);
|
|
if (ret < 0)
|
|
dev_dbg(dev, "pm_runtime_put_sync failed\n");
|
|
|
|
pm_runtime_disable(dev);
|
|
dra7xx_pcie_disable_phy(dra7xx);
|
|
|
|
clk_disable_unprepare(dra7xx->clk);
|
|
}
|
|
|
|
static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
|
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
|
|
dra7xx_pcie_resume_noirq)
|
|
};
|
|
|
|
static struct platform_driver dra7xx_pcie_driver = {
|
|
.probe = dra7xx_pcie_probe,
|
|
.driver = {
|
|
.name = "dra7-pcie",
|
|
.of_match_table = of_dra7xx_pcie_match,
|
|
.suppress_bind_attrs = true,
|
|
.pm = &dra7xx_pcie_pm_ops,
|
|
},
|
|
.shutdown = dra7xx_pcie_shutdown,
|
|
};
|
|
module_platform_driver(dra7xx_pcie_driver);
|
|
|
|
MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
|
|
MODULE_DESCRIPTION("PCIe controller driver for TI DRA7xx SoCs");
|
|
MODULE_LICENSE("GPL v2");
|