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-----BEGIN PGP SIGNATURE----- iQJIBAABCgAyFiEEgMe7l+5h9hnxdsnuWYigwDrT+vwFAmHgpugUHGJoZWxnYWFz QGdvb2dsZS5jb20ACgkQWYigwDrT+vz59g//eWRLb0j2Vgv84ZH4x1iv6MaBboQr 2wScnfoN+MIoh+tuM4kRak15X4nB8rJhNZZCzesMUN6PeZvrkoPo4sz/xdzIrA/N qY3h8NZ3nC4yCvs/tGem0zZUcSCJsxUAD0eegyMSa142xGIOQTHBSJRflR9osKSo bnQlKTkugV8t4kD7NlQ5M3HzN3R+mjsII5JNzCqv2XlzAZG3D8DhPyIpZnRNAOmW KiHOVXvQOocfUlvSs5kBlhgR1HgJkGnruCrJ1iDCWQH1Zk0iuVgoZWgVda6Cs3Xv gcTJLB7VoSdNZKnct9aMNYPKziHkYc7clilPeDsJs5TlSv3kKERzLj6c/5ZAxFWN +RsH+zYHDXJSsL/w0twPnaF5WCuVYUyrs3UiSjUvShKl1T9k9J+Jo8zwUUZx8Xb0 qXX8jRGMHolBGwPXm2fHEb4bwTUI8emPj29qK4L96KsQ3zKXWB8eGSosxUP52Tti RR2WZjkvwlREZCJp6jSEJYkhzoEaVAm8CjKpKUuneX9WcUOsMBSs9k7EXbUy7JeM hq5Keuqa8PZo/IK2DYYAchNnBJUDMsWJeduBW12qSmx3J+9victP2qOFu+9skP0a 85xlO6Cx8beiQh+XnY7jyROvIFuxTnGKHgkq/89Ham/whEzdJ+GRIiYB218kLLCW ILdas3C2iiGz99I= =Vgg4 -----END PGP SIGNATURE----- Merge tag 'pci-v5.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull pci updates from Bjorn Helgaas: "Enumeration: - Use pci_find_vsec_capability() instead of open-coding it (Andy Shevchenko) - Convert pci_dev_present() stub from macro to static inline to avoid 'unused variable' errors (Hans de Goede) - Convert sysfs slot attributes from default_attrs to default_groups (Greg Kroah-Hartman) - Use DWORD accesses for LTR, L1 SS to avoid BayHub OZ711LV2 erratum (Rajat Jain) - Remove unnecessary initialization of static variables (Longji Guo) Resource management: - Always write Intel I210 ROM BAR on update to work around device defect (Bjorn Helgaas) PCIe native device hotplug: - Fix pciehp lockdep errors on Thunderbolt undock (Hans de Goede) - Fix infinite loop in pciehp IRQ handler on power fault (Lukas Wunner) Power management: - Convert amd64-agp, sis-agp, via-agp from legacy PCI power management to generic power management (Vaibhav Gupta) IOMMU: - Add function 1 DMA alias quirk for Marvell 88SE9125 SATA controller so it can work with an IOMMU (Yifeng Li) Error handling: - Add PCI_ERROR_RESPONSE and related definitions for signaling and checking for transaction errors on PCI (Naveen Naidu) - Fabricate PCI_ERROR_RESPONSE data (~0) in config read wrappers, instead of in host controller drivers, when transactions fail on PCI (Naveen Naidu) - Use PCI_POSSIBLE_ERROR() to check for possible failure of config reads (Naveen Naidu) Peer-to-peer DMA: - Add Logan Gunthorpe as P2PDMA maintainer (Bjorn Helgaas) ASPM: - Calculate link L0s and L1 exit latencies when needed instead of caching them (Saheed O. Bolarinwa) - Calculate device L0s and L1 acceptable exit latencies when needed instead of caching them (Saheed O. Bolarinwa) - Remove struct aspm_latency since it's no longer needed (Saheed O. Bolarinwa) APM X-Gene PCIe controller driver: - Fix IB window setup, which was broken by the fact that IB resources are now sorted in address order instead of DT dma-ranges order (Rob Herring) Apple PCIe controller driver: - Enable clock gating to save power (Hector Martin) - Fix REFCLK1 enable/poll logic (Hector Martin) Broadcom STB PCIe controller driver: - Declare bitmap correctly for use by bitmap interfaces (Christophe JAILLET) - Clean up computation of legacy and non-legacy MSI bitmasks (Florian Fainelli) - Update suspend/resume/remove error handling to warn about errors and not fail the operation (Jim Quinlan) - Correct the "pcie" and "msi" interrupt descriptions in DT binding (Jim Quinlan) - Add DT bindings for endpoint voltage regulators (Jim Quinlan) - Split brcm_pcie_setup() into two functions (Jim Quinlan) - Add mechanism for turning on voltage regulators for connected devices (Jim Quinlan) - Turn voltage regulators for connected devices on/off when bus is added or removed (Jim Quinlan) - When suspending, don't turn off voltage regulators for wakeup devices (Jim Quinlan) Freescale i.MX6 PCIe controller driver: - Add i.MX8MM support (Richard Zhu) Freescale Layerscape PCIe controller driver: - Use DWC common ops instead of layerscape-specific link-up functions (Hou Zhiqiang) Intel VMD host bridge driver: - Honor platform ACPI _OSC feature negotiation for Root Ports below VMD (Kai-Heng Feng) - Add support for Raptor Lake SKUs (Karthik L Gopalakrishnan) - Reset everything below VMD before enumerating to work around failure to enumerate NVMe devices when guest OS reboots (Nirmal Patel) Bridge emulation (used by Marvell Aardvark and MVEBU): - Make emulated ROM BAR read-only by default (Pali Rohár) - Make some emulated legacy PCI bits read-only for PCIe devices (Pali Rohár) - Update reserved bits in emulated PCIe Capability (Pali Rohár) - Allow drivers to emulate different PCIe Capability versions (Pali Rohár) - Set emulated Capabilities List bit for all PCIe devices, since they must have at least a PCIe Capability (Pali Rohár) Marvell Aardvark PCIe controller driver: - Add bridge emulation definitions for PCIe DEVCAP2, DEVCTL2, DEVSTA2, LNKCAP2, LNKCTL2, LNKSTA2, SLTCAP2, SLTCTL2, SLTSTA2 (Pali Rohár) - Add aardvark support for DEVCAP2, DEVCTL2, LNKCAP2 and LNKCTL2 registers (Pali Rohár) - Clear all MSIs at setup to avoid spurious interrupts (Pali Rohár) - Disable bus mastering when unbinding host controller driver (Pali Rohár) - Mask all interrupts when unbinding host controller driver (Pali Rohár) - Fix memory leak in host controller unbind (Pali Rohár) - Assert PERST# when unbinding host controller driver (Pali Rohár) - Disable link training when unbinding host controller driver (Pali Rohár) - Disable common PHY when unbinding host controller driver (Pali Rohár) - Fix resource type checking to check only IORESOURCE_MEM, not IORESOURCE_MEM_64, which is a flavor of IORESOURCE_MEM (Pali Rohár) Marvell MVEBU PCIe controller driver: - Implement pci_remap_iospace() for ARM so mvebu can use devm_pci_remap_iospace() instead of the previous ARM-specific pci_ioremap_io() interface (Pali Rohár) - Use the standard pci_host_probe() instead of the device-specific mvebu_pci_host_probe() (Pali Rohár) - Replace all uses of ARM-specific pci_ioremap_io() with the ARM implementation of the standard pci_remap_iospace() interface and remove pci_ioremap_io() (Pali Rohár) - Skip initializing invalid Root Ports (Pali Rohár) - Check for errors from pci_bridge_emul_init() (Pali Rohár) - Ignore any bridges at non-zero function numbers (Pali Rohár) - Return ~0 data for invalid config read size (Pali Rohár) - Disallow mapping interrupts on emulated bridges (Pali Rohár) - Clear Root Port Memory & I/O Space Enable and Bus Master Enable at initialization (Pali Rohár) - Make type bits in Root Port I/O Base register read-only (Pali Rohár) - Disable Root Port windows when base/limit set to invalid values (Pali Rohár) - Set controller to Root Complex mode (Pali Rohár) - Set Root Port Class Code to PCI Bridge (Pali Rohár) - Update emulated Root Port secondary bus numbers to better reflect the actual topology (Pali Rohár) - Add PCI_BRIDGE_CTL_BUS_RESET support to emulated Root Ports so pci_reset_secondary_bus() can reset connected devices (Pali Rohár) - Add PCI_EXP_DEVCTL Error Reporting Enable support to emulated Root Ports (Pali Rohár) - Add PCI_EXP_RTSTA PME Status bit support to emulated Root Ports (Pali Rohár) - Add DEVCAP2, DEVCTL2 and LNKCTL2 support to emulated Root Ports on Armada XP and newer devices (Pali Rohár) - Export mvebu-mbus.c symbols to allow pci-mvebu.c to be a module (Pali Rohár) - Add support for compiling as a module (Pali Rohár) MediaTek PCIe controller driver: - Assert PERST# for 100ms to allow power and clock to stabilize (qizhong cheng) MediaTek PCIe Gen3 controller driver: - Disable Mediatek DVFSRC voltage request since lack of DVFSRC to respond to the request causes failure to exit L1 PM Substate (Jianjun Wang) MediaTek MT7621 PCIe controller driver: - Declare mt7621_pci_ops static (Sergio Paracuellos) - Give pcibios_root_bridge_prepare() access to host bridge windows (Sergio Paracuellos) - Move MIPS I/O coherency unit setup from driver to pcibios_root_bridge_prepare() (Sergio Paracuellos) - Add missing MODULE_LICENSE() (Sergio Paracuellos) - Allow COMPILE_TEST for all arches (Sergio Paracuellos) Microsoft Hyper-V host bridge driver: - Add hv-internal interfaces to encapsulate arch IRQ dependencies (Sunil Muthuswamy) - Add arm64 Hyper-V vPCI support (Sunil Muthuswamy) Qualcomm PCIe controller driver: - Undo PM setup in qcom_pcie_probe() error handling path (Christophe JAILLET) - Use __be16 type to store return value from cpu_to_be16() (Manivannan Sadhasivam) - Constify static dw_pcie_ep_ops (Rikard Falkeborn) Renesas R-Car PCIe controller driver: - Fix aarch32 abort handler so it doesn't check the wrong bus clock before accessing the host controller (Marek Vasut) TI Keystone PCIe controller driver: - Add register offset for ti,syscon-pcie-id and ti,syscon-pcie-mode DT properties (Kishon Vijay Abraham I) MicroSemi Switchtec management driver: - Add Gen4 automotive device IDs (Kelvin Cao) - Declare state_names[] as static so it's not allocated and initialized for every call (Kelvin Cao) Host controller driver cleanups: - Use of_device_get_match_data(), not of_match_device(), when we only need the device data in altera, artpec6, cadence, designware-plat, dra7xx, keystone, kirin (Fan Fei) - Drop pointless of_device_get_match_data() cast in j721e (Bjorn Helgaas) - Drop redundant struct device * from j721e since struct cdns_pcie already has one (Bjorn Helgaas) - Rename driver structs to *_pcie in intel-gw, iproc, ls-gen4, mediatek-gen3, microchip, mt7621, rcar-gen2, tegra194, uniphier, xgene, xilinx, xilinx-cpm for consistency across drivers (Fan Fei) - Fix invalid address space conversions in hisi, spear13xx (Bjorn Helgaas) Miscellaneous: - Sort Intel Device IDs by value (Andy Shevchenko) - Change Capability offsets to hex to match spec (Baruch Siach) - Correct misspellings (Krzysztof Wilczyński) - Terminate statement with semicolon in pci_endpoint_test.c (Ming Wang)" * tag 'pci-v5.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (151 commits) PCI: mt7621: Allow COMPILE_TEST for all arches PCI: mt7621: Add missing MODULE_LICENSE() PCI: mt7621: Move MIPS setup to pcibios_root_bridge_prepare() PCI: Let pcibios_root_bridge_prepare() access bridge->windows PCI: mt7621: Declare mt7621_pci_ops static PCI: brcmstb: Do not turn off WOL regulators on suspend PCI: brcmstb: Add control of subdevice voltage regulators PCI: brcmstb: Add mechanism to turn on subdev regulators PCI: brcmstb: Split brcm_pcie_setup() into two funcs dt-bindings: PCI: Add bindings for Brcmstb EP voltage regulators dt-bindings: PCI: Correct brcmstb interrupts, interrupt-map. PCI: brcmstb: Fix function return value handling PCI: brcmstb: Do not use __GENMASK PCI: brcmstb: Declare 'used' as bitmap, not unsigned long PCI: hv: Add arm64 Hyper-V vPCI support PCI: hv: Make the code arch neutral by adding arch specific interfaces PCI: pciehp: Use down_read/write_nested(reset_lock) to fix lockdep errors x86/PCI: Remove initialization of static variables to false PCI: Use DWORD accesses for LTR, L1 SS to avoid erratum misc: pci_endpoint_test: Terminate statement with semicolon ...
444 lines
11 KiB
C
444 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for Samsung Exynos SoCs
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*
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* Copyright (C) 2013-2020 Samsung Electronics Co., Ltd.
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* https://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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* Jaehoon Chung <jh80.chung@samsung.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_device.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/phy/phy.h>
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#include <linux/regulator/consumer.h>
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#include <linux/module.h>
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#include "pcie-designware.h"
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#define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
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/* PCIe ELBI registers */
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#define PCIE_IRQ_PULSE 0x000
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#define IRQ_INTA_ASSERT BIT(0)
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#define IRQ_INTB_ASSERT BIT(2)
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#define IRQ_INTC_ASSERT BIT(4)
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#define IRQ_INTD_ASSERT BIT(6)
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#define PCIE_IRQ_LEVEL 0x004
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#define PCIE_IRQ_SPECIAL 0x008
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#define PCIE_IRQ_EN_PULSE 0x00c
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#define PCIE_IRQ_EN_LEVEL 0x010
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#define PCIE_IRQ_EN_SPECIAL 0x014
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#define PCIE_SW_WAKE 0x018
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#define PCIE_BUS_EN BIT(1)
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#define PCIE_CORE_RESET 0x01c
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#define PCIE_CORE_RESET_ENABLE BIT(0)
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#define PCIE_STICKY_RESET 0x020
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#define PCIE_NONSTICKY_RESET 0x024
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#define PCIE_APP_INIT_RESET 0x028
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#define PCIE_APP_LTSSM_ENABLE 0x02c
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#define PCIE_ELBI_RDLH_LINKUP 0x074
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#define PCIE_ELBI_XMLH_LINKUP BIT(4)
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#define PCIE_ELBI_LTSSM_ENABLE 0x1
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#define PCIE_ELBI_SLV_AWMISC 0x11c
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#define PCIE_ELBI_SLV_ARMISC 0x120
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#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21)
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struct exynos_pcie {
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struct dw_pcie pci;
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void __iomem *elbi_base;
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struct clk *clk;
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struct clk *bus_clk;
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struct phy *phy;
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struct regulator_bulk_data supplies[2];
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};
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static int exynos_pcie_init_clk_resources(struct exynos_pcie *ep)
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{
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struct device *dev = ep->pci.dev;
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int ret;
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ret = clk_prepare_enable(ep->clk);
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if (ret) {
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dev_err(dev, "cannot enable pcie rc clock");
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return ret;
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}
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ret = clk_prepare_enable(ep->bus_clk);
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if (ret) {
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dev_err(dev, "cannot enable pcie bus clock");
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goto err_bus_clk;
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}
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return 0;
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err_bus_clk:
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clk_disable_unprepare(ep->clk);
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return ret;
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}
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static void exynos_pcie_deinit_clk_resources(struct exynos_pcie *ep)
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{
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clk_disable_unprepare(ep->bus_clk);
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clk_disable_unprepare(ep->clk);
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}
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static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
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{
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writel(val, base + reg);
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}
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static u32 exynos_pcie_readl(void __iomem *base, u32 reg)
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{
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return readl(base + reg);
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}
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static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on)
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{
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u32 val;
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val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
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if (on)
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val |= PCIE_ELBI_SLV_DBI_ENABLE;
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else
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val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
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exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
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}
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static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on)
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{
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u32 val;
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val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
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if (on)
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val |= PCIE_ELBI_SLV_DBI_ENABLE;
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else
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val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
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exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
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}
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static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep)
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{
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u32 val;
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val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
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val &= ~PCIE_CORE_RESET_ENABLE;
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exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
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exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET);
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exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET);
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}
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static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep)
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{
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u32 val;
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val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
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val |= PCIE_CORE_RESET_ENABLE;
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exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
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exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET);
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exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET);
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exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET);
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exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET);
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}
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static int exynos_pcie_start_link(struct dw_pcie *pci)
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{
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struct exynos_pcie *ep = to_exynos_pcie(pci);
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u32 val;
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val = exynos_pcie_readl(ep->elbi_base, PCIE_SW_WAKE);
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val &= ~PCIE_BUS_EN;
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exynos_pcie_writel(ep->elbi_base, val, PCIE_SW_WAKE);
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/* assert LTSSM enable */
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exynos_pcie_writel(ep->elbi_base, PCIE_ELBI_LTSSM_ENABLE,
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PCIE_APP_LTSSM_ENABLE);
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return 0;
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}
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static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep)
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{
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u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE);
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exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE);
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}
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static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
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{
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struct exynos_pcie *ep = arg;
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exynos_pcie_clear_irq_pulse(ep);
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return IRQ_HANDLED;
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}
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static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
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{
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u32 val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
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IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
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exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE);
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exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL);
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exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_SPECIAL);
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}
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static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
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u32 reg, size_t size)
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{
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struct exynos_pcie *ep = to_exynos_pcie(pci);
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u32 val;
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exynos_pcie_sideband_dbi_r_mode(ep, true);
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dw_pcie_read(base + reg, size, &val);
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exynos_pcie_sideband_dbi_r_mode(ep, false);
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return val;
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}
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static void exynos_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
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u32 reg, size_t size, u32 val)
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{
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struct exynos_pcie *ep = to_exynos_pcie(pci);
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exynos_pcie_sideband_dbi_w_mode(ep, true);
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dw_pcie_write(base + reg, size, val);
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exynos_pcie_sideband_dbi_w_mode(ep, false);
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}
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static int exynos_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
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if (PCI_SLOT(devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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*val = dw_pcie_read_dbi(pci, where, size);
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return PCIBIOS_SUCCESSFUL;
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}
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static int exynos_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
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if (PCI_SLOT(devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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dw_pcie_write_dbi(pci, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops exynos_pci_ops = {
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.read = exynos_pcie_rd_own_conf,
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.write = exynos_pcie_wr_own_conf,
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};
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static int exynos_pcie_link_up(struct dw_pcie *pci)
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{
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struct exynos_pcie *ep = to_exynos_pcie(pci);
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u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP);
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return (val & PCIE_ELBI_XMLH_LINKUP);
|
|
}
|
|
|
|
static int exynos_pcie_host_init(struct pcie_port *pp)
|
|
{
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
|
struct exynos_pcie *ep = to_exynos_pcie(pci);
|
|
|
|
pp->bridge->ops = &exynos_pci_ops;
|
|
|
|
exynos_pcie_assert_core_reset(ep);
|
|
|
|
phy_reset(ep->phy);
|
|
phy_power_on(ep->phy);
|
|
phy_init(ep->phy);
|
|
|
|
exynos_pcie_deassert_core_reset(ep);
|
|
exynos_pcie_enable_irq_pulse(ep);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dw_pcie_host_ops exynos_pcie_host_ops = {
|
|
.host_init = exynos_pcie_host_init,
|
|
};
|
|
|
|
static int exynos_add_pcie_port(struct exynos_pcie *ep,
|
|
struct platform_device *pdev)
|
|
{
|
|
struct dw_pcie *pci = &ep->pci;
|
|
struct pcie_port *pp = &pci->pp;
|
|
struct device *dev = &pdev->dev;
|
|
int ret;
|
|
|
|
pp->irq = platform_get_irq(pdev, 0);
|
|
if (pp->irq < 0)
|
|
return pp->irq;
|
|
|
|
ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler,
|
|
IRQF_SHARED, "exynos-pcie", ep);
|
|
if (ret) {
|
|
dev_err(dev, "failed to request irq\n");
|
|
return ret;
|
|
}
|
|
|
|
pp->ops = &exynos_pcie_host_ops;
|
|
pp->msi_irq = -ENODEV;
|
|
|
|
ret = dw_pcie_host_init(pp);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize host\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dw_pcie_ops dw_pcie_ops = {
|
|
.read_dbi = exynos_pcie_read_dbi,
|
|
.write_dbi = exynos_pcie_write_dbi,
|
|
.link_up = exynos_pcie_link_up,
|
|
.start_link = exynos_pcie_start_link,
|
|
};
|
|
|
|
static int exynos_pcie_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct exynos_pcie *ep;
|
|
struct device_node *np = dev->of_node;
|
|
int ret;
|
|
|
|
ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
|
|
if (!ep)
|
|
return -ENOMEM;
|
|
|
|
ep->pci.dev = dev;
|
|
ep->pci.ops = &dw_pcie_ops;
|
|
|
|
ep->phy = devm_of_phy_get(dev, np, NULL);
|
|
if (IS_ERR(ep->phy))
|
|
return PTR_ERR(ep->phy);
|
|
|
|
/* External Local Bus interface (ELBI) registers */
|
|
ep->elbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi");
|
|
if (IS_ERR(ep->elbi_base))
|
|
return PTR_ERR(ep->elbi_base);
|
|
|
|
ep->clk = devm_clk_get(dev, "pcie");
|
|
if (IS_ERR(ep->clk)) {
|
|
dev_err(dev, "Failed to get pcie rc clock\n");
|
|
return PTR_ERR(ep->clk);
|
|
}
|
|
|
|
ep->bus_clk = devm_clk_get(dev, "pcie_bus");
|
|
if (IS_ERR(ep->bus_clk)) {
|
|
dev_err(dev, "Failed to get pcie bus clock\n");
|
|
return PTR_ERR(ep->bus_clk);
|
|
}
|
|
|
|
ep->supplies[0].supply = "vdd18";
|
|
ep->supplies[1].supply = "vdd10";
|
|
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ep->supplies),
|
|
ep->supplies);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = exynos_pcie_init_clk_resources(ep);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies);
|
|
if (ret)
|
|
return ret;
|
|
|
|
platform_set_drvdata(pdev, ep);
|
|
|
|
ret = exynos_add_pcie_port(ep, pdev);
|
|
if (ret < 0)
|
|
goto fail_probe;
|
|
|
|
return 0;
|
|
|
|
fail_probe:
|
|
phy_exit(ep->phy);
|
|
exynos_pcie_deinit_clk_resources(ep);
|
|
regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __exit exynos_pcie_remove(struct platform_device *pdev)
|
|
{
|
|
struct exynos_pcie *ep = platform_get_drvdata(pdev);
|
|
|
|
dw_pcie_host_deinit(&ep->pci.pp);
|
|
exynos_pcie_assert_core_reset(ep);
|
|
phy_power_off(ep->phy);
|
|
phy_exit(ep->phy);
|
|
exynos_pcie_deinit_clk_resources(ep);
|
|
regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused exynos_pcie_suspend_noirq(struct device *dev)
|
|
{
|
|
struct exynos_pcie *ep = dev_get_drvdata(dev);
|
|
|
|
exynos_pcie_assert_core_reset(ep);
|
|
phy_power_off(ep->phy);
|
|
phy_exit(ep->phy);
|
|
regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused exynos_pcie_resume_noirq(struct device *dev)
|
|
{
|
|
struct exynos_pcie *ep = dev_get_drvdata(dev);
|
|
struct dw_pcie *pci = &ep->pci;
|
|
struct pcie_port *pp = &pci->pp;
|
|
int ret;
|
|
|
|
ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* exynos_pcie_host_init controls ep->phy */
|
|
exynos_pcie_host_init(pp);
|
|
dw_pcie_setup_rc(pp);
|
|
exynos_pcie_start_link(pci);
|
|
return dw_pcie_wait_for_link(pci);
|
|
}
|
|
|
|
static const struct dev_pm_ops exynos_pcie_pm_ops = {
|
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos_pcie_suspend_noirq,
|
|
exynos_pcie_resume_noirq)
|
|
};
|
|
|
|
static const struct of_device_id exynos_pcie_of_match[] = {
|
|
{ .compatible = "samsung,exynos5433-pcie", },
|
|
{ },
|
|
};
|
|
|
|
static struct platform_driver exynos_pcie_driver = {
|
|
.probe = exynos_pcie_probe,
|
|
.remove = __exit_p(exynos_pcie_remove),
|
|
.driver = {
|
|
.name = "exynos-pcie",
|
|
.of_match_table = exynos_pcie_of_match,
|
|
.pm = &exynos_pcie_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(exynos_pcie_driver);
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DEVICE_TABLE(of, exynos_pcie_of_match);
|