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![Pali Rohár](/assets/img/avatar_default.png)
Add these PCI class codes to pci_ids.h: PCI_CLASS_BRIDGE_PCI_NORMAL PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE Use these defines in all kernel code for describing PCI class codes for normal and subtractive PCI bridges. [bhelgaas: similar change in pci-mvebu.c] Link: https://lore.kernel.org/r/20220214114109.26809-1-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
492 lines
11 KiB
C
492 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for Amlogic MESON SoCs
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*
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* Copyright (c) 2018 Amlogic, inc.
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* Author: Yue Wang <yue.wang@amlogic.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/resource.h>
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#include <linux/types.h>
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#include <linux/phy/phy.h>
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#include <linux/module.h>
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#include "pcie-designware.h"
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#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
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#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
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#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
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/* PCIe specific config registers */
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#define PCIE_CFG0 0x0
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#define APP_LTSSM_ENABLE BIT(7)
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#define PCIE_CFG_STATUS12 0x30
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#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
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#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
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#define IS_LTSSM_UP(x) ((((x) >> 10) & 0x1f) == 0x11)
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#define PCIE_CFG_STATUS17 0x44
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#define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1)
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#define WAIT_LINKUP_TIMEOUT 4000
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#define PORT_CLK_RATE 100000000UL
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#define MAX_PAYLOAD_SIZE 256
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#define MAX_READ_REQ_SIZE 256
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#define PCIE_RESET_DELAY 500
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#define PCIE_SHARED_RESET 1
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#define PCIE_NORMAL_RESET 0
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enum pcie_data_rate {
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PCIE_GEN1,
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PCIE_GEN2,
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PCIE_GEN3,
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PCIE_GEN4
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};
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struct meson_pcie_clk_res {
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struct clk *clk;
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struct clk *port_clk;
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struct clk *general_clk;
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};
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struct meson_pcie_rc_reset {
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struct reset_control *port;
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struct reset_control *apb;
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};
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struct meson_pcie {
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struct dw_pcie pci;
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void __iomem *cfg_base;
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struct meson_pcie_clk_res clk_res;
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struct meson_pcie_rc_reset mrst;
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struct gpio_desc *reset_gpio;
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struct phy *phy;
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};
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static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
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const char *id,
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u32 reset_type)
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{
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struct device *dev = mp->pci.dev;
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struct reset_control *reset;
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if (reset_type == PCIE_SHARED_RESET)
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reset = devm_reset_control_get_shared(dev, id);
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else
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reset = devm_reset_control_get(dev, id);
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return reset;
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}
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static int meson_pcie_get_resets(struct meson_pcie *mp)
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{
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struct meson_pcie_rc_reset *mrst = &mp->mrst;
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mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
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if (IS_ERR(mrst->port))
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return PTR_ERR(mrst->port);
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reset_control_deassert(mrst->port);
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mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET);
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if (IS_ERR(mrst->apb))
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return PTR_ERR(mrst->apb);
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reset_control_deassert(mrst->apb);
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return 0;
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}
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static int meson_pcie_get_mems(struct platform_device *pdev,
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struct meson_pcie *mp)
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{
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struct dw_pcie *pci = &mp->pci;
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pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi");
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if (IS_ERR(pci->dbi_base))
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return PTR_ERR(pci->dbi_base);
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mp->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
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if (IS_ERR(mp->cfg_base))
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return PTR_ERR(mp->cfg_base);
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return 0;
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}
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static int meson_pcie_power_on(struct meson_pcie *mp)
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{
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int ret = 0;
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ret = phy_init(mp->phy);
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if (ret)
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return ret;
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ret = phy_power_on(mp->phy);
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if (ret) {
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phy_exit(mp->phy);
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return ret;
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}
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return 0;
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}
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static void meson_pcie_power_off(struct meson_pcie *mp)
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{
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phy_power_off(mp->phy);
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phy_exit(mp->phy);
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}
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static int meson_pcie_reset(struct meson_pcie *mp)
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{
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struct meson_pcie_rc_reset *mrst = &mp->mrst;
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int ret = 0;
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ret = phy_reset(mp->phy);
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if (ret)
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return ret;
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reset_control_assert(mrst->port);
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reset_control_assert(mrst->apb);
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udelay(PCIE_RESET_DELAY);
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reset_control_deassert(mrst->port);
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reset_control_deassert(mrst->apb);
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udelay(PCIE_RESET_DELAY);
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return 0;
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}
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static inline struct clk *meson_pcie_probe_clock(struct device *dev,
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const char *id, u64 rate)
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{
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struct clk *clk;
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int ret;
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clk = devm_clk_get(dev, id);
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if (IS_ERR(clk))
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return clk;
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if (rate) {
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ret = clk_set_rate(clk, rate);
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if (ret) {
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dev_err(dev, "set clk rate failed, ret = %d\n", ret);
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return ERR_PTR(ret);
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}
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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dev_err(dev, "couldn't enable clk\n");
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return ERR_PTR(ret);
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}
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devm_add_action_or_reset(dev,
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(void (*) (void *))clk_disable_unprepare,
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clk);
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return clk;
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}
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static int meson_pcie_probe_clocks(struct meson_pcie *mp)
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{
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struct device *dev = mp->pci.dev;
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struct meson_pcie_clk_res *res = &mp->clk_res;
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res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE);
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if (IS_ERR(res->port_clk))
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return PTR_ERR(res->port_clk);
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res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
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if (IS_ERR(res->general_clk))
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return PTR_ERR(res->general_clk);
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res->clk = meson_pcie_probe_clock(dev, "pclk", 0);
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if (IS_ERR(res->clk))
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return PTR_ERR(res->clk);
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return 0;
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}
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static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg)
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{
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return readl(mp->cfg_base + reg);
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}
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static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
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{
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writel(val, mp->cfg_base + reg);
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}
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static void meson_pcie_assert_reset(struct meson_pcie *mp)
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{
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gpiod_set_value_cansleep(mp->reset_gpio, 1);
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udelay(500);
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gpiod_set_value_cansleep(mp->reset_gpio, 0);
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}
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static void meson_pcie_ltssm_enable(struct meson_pcie *mp)
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{
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u32 val;
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val = meson_cfg_readl(mp, PCIE_CFG0);
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val |= APP_LTSSM_ENABLE;
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meson_cfg_writel(mp, val, PCIE_CFG0);
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}
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static int meson_size_to_payload(struct meson_pcie *mp, int size)
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{
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struct device *dev = mp->pci.dev;
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/*
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* dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
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* So if input size is not 2^order alignment or less than 2^7 or bigger
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* than 2^12, just set to default size 2^(1+7).
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*/
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if (!is_power_of_2(size) || size < 128 || size > 4096) {
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dev_warn(dev, "payload size %d, set to default 256\n", size);
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return 1;
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}
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return fls(size) - 8;
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}
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static void meson_set_max_payload(struct meson_pcie *mp, int size)
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{
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struct dw_pcie *pci = &mp->pci;
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u32 val;
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u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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int max_payload_size = meson_size_to_payload(mp, size);
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val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
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val &= ~PCI_EXP_DEVCTL_PAYLOAD;
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dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
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val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
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val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
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dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
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}
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static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
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{
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struct dw_pcie *pci = &mp->pci;
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u32 val;
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u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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int max_rd_req_size = meson_size_to_payload(mp, size);
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val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
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val &= ~PCI_EXP_DEVCTL_READRQ;
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dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
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val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
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val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
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dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
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}
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static int meson_pcie_start_link(struct dw_pcie *pci)
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{
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struct meson_pcie *mp = to_meson_pcie(pci);
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meson_pcie_ltssm_enable(mp);
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meson_pcie_assert_reset(mp);
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return 0;
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}
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static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn,
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int where, int size, u32 *val)
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{
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int ret;
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ret = pci_generic_config_read(bus, devfn, where, size, val);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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/*
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* There is a bug in the MESON AXG PCIe controller whereby software
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* cannot program the PCI_CLASS_DEVICE register, so we must fabricate
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* the return value in the config accessors.
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*/
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if ((where & ~3) == PCI_CLASS_REVISION) {
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if (size <= 2)
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*val = (*val & ((1 << (size * 8)) - 1)) << (8 * (where & 3));
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*val &= ~0xffffff00;
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*val |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
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if (size <= 2)
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*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops meson_pci_ops = {
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.map_bus = dw_pcie_own_conf_map_bus,
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.read = meson_pcie_rd_own_conf,
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.write = pci_generic_config_write,
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};
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static int meson_pcie_link_up(struct dw_pcie *pci)
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{
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struct meson_pcie *mp = to_meson_pcie(pci);
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struct device *dev = pci->dev;
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u32 speed_okay = 0;
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u32 cnt = 0;
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u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
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do {
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state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
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state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
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smlh_up = IS_SMLH_LINK_UP(state12);
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rdlh_up = IS_RDLH_LINK_UP(state12);
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ltssm_up = IS_LTSSM_UP(state12);
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if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
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speed_okay = 1;
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if (smlh_up)
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dev_dbg(dev, "smlh_link_up is on\n");
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if (rdlh_up)
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dev_dbg(dev, "rdlh_link_up is on\n");
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if (ltssm_up)
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dev_dbg(dev, "ltssm_up is on\n");
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if (speed_okay)
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dev_dbg(dev, "speed_okay\n");
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if (smlh_up && rdlh_up && ltssm_up && speed_okay)
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return 1;
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cnt++;
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udelay(10);
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} while (cnt < WAIT_LINKUP_TIMEOUT);
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dev_err(dev, "error: wait linkup timeout\n");
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return 0;
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}
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static int meson_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct meson_pcie *mp = to_meson_pcie(pci);
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pp->bridge->ops = &meson_pci_ops;
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meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
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meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
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return 0;
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}
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static const struct dw_pcie_host_ops meson_pcie_host_ops = {
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.host_init = meson_pcie_host_init,
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};
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static const struct dw_pcie_ops dw_pcie_ops = {
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.link_up = meson_pcie_link_up,
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.start_link = meson_pcie_start_link,
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};
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static int meson_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct dw_pcie *pci;
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struct meson_pcie *mp;
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int ret;
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mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
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if (!mp)
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return -ENOMEM;
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pci = &mp->pci;
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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pci->pp.ops = &meson_pcie_host_ops;
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pci->num_lanes = 1;
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mp->phy = devm_phy_get(dev, "pcie");
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if (IS_ERR(mp->phy)) {
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dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
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return PTR_ERR(mp->phy);
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}
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mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
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if (IS_ERR(mp->reset_gpio)) {
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dev_err(dev, "get reset gpio failed\n");
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return PTR_ERR(mp->reset_gpio);
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}
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ret = meson_pcie_get_resets(mp);
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if (ret) {
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dev_err(dev, "get reset resource failed, %d\n", ret);
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return ret;
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}
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ret = meson_pcie_get_mems(pdev, mp);
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if (ret) {
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dev_err(dev, "get memory resource failed, %d\n", ret);
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return ret;
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}
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ret = meson_pcie_power_on(mp);
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if (ret) {
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dev_err(dev, "phy power on failed, %d\n", ret);
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return ret;
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}
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ret = meson_pcie_reset(mp);
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if (ret) {
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dev_err(dev, "reset failed, %d\n", ret);
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goto err_phy;
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}
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ret = meson_pcie_probe_clocks(mp);
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if (ret) {
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dev_err(dev, "init clock resources failed, %d\n", ret);
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goto err_phy;
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}
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platform_set_drvdata(pdev, mp);
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ret = dw_pcie_host_init(&pci->pp);
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if (ret < 0) {
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dev_err(dev, "Add PCIe port failed, %d\n", ret);
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goto err_phy;
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}
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return 0;
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err_phy:
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meson_pcie_power_off(mp);
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return ret;
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}
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static const struct of_device_id meson_pcie_of_match[] = {
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{
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.compatible = "amlogic,axg-pcie",
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},
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{
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.compatible = "amlogic,g12a-pcie",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, meson_pcie_of_match);
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static struct platform_driver meson_pcie_driver = {
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.probe = meson_pcie_probe,
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.driver = {
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.name = "meson-pcie",
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.of_match_table = meson_pcie_of_match,
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},
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};
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module_platform_driver(meson_pcie_driver);
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MODULE_AUTHOR("Yue Wang <yue.wang@amlogic.com>");
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MODULE_DESCRIPTION("Amlogic PCIe Controller driver");
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MODULE_LICENSE("GPL v2");
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