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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
![Jiantao Zhang](/assets/img/avatar_default.png)
When dma_mapping_error() returns error because of no enough memory,
but dw_pcie_host_init() returns success, which will mislead the callers.
Link: https://lore.kernel.org/r/30170911-0e2f-98ce-9266-70465b9073e5@huawei.com
Fixes: 07940c369a
("PCI: dwc: Fix MSI page leakage in suspend/resume")
Signed-off-by: Jianrong Zhang <zhangjianrong5@huawei.com>
Signed-off-by: Jiantao Zhang <water.zhangjiantao@huawei.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
637 lines
16 KiB
C
637 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Synopsys DesignWare PCIe host controller driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* https://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*/
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/msi.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/pci_regs.h>
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#include <linux/platform_device.h>
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#include "../../pci.h"
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#include "pcie-designware.h"
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static struct pci_ops dw_pcie_ops;
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static struct pci_ops dw_child_pcie_ops;
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static void dw_msi_ack_irq(struct irq_data *d)
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{
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irq_chip_ack_parent(d);
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}
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static void dw_msi_mask_irq(struct irq_data *d)
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{
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pci_msi_mask_irq(d);
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irq_chip_mask_parent(d);
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}
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static void dw_msi_unmask_irq(struct irq_data *d)
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{
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pci_msi_unmask_irq(d);
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irq_chip_unmask_parent(d);
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}
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static struct irq_chip dw_pcie_msi_irq_chip = {
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.name = "PCI-MSI",
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.irq_ack = dw_msi_ack_irq,
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.irq_mask = dw_msi_mask_irq,
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.irq_unmask = dw_msi_unmask_irq,
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};
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static struct msi_domain_info dw_pcie_msi_domain_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
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.chip = &dw_pcie_msi_irq_chip,
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};
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/* MSI int handler */
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irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
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{
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int i, pos;
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unsigned long val;
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u32 status, num_ctrls;
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irqreturn_t ret = IRQ_NONE;
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
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for (i = 0; i < num_ctrls; i++) {
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status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
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(i * MSI_REG_CTRL_BLOCK_SIZE));
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if (!status)
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continue;
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ret = IRQ_HANDLED;
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val = status;
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pos = 0;
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while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
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pos)) != MAX_MSI_IRQS_PER_CTRL) {
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generic_handle_domain_irq(pp->irq_domain,
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(i * MAX_MSI_IRQS_PER_CTRL) +
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pos);
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pos++;
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}
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}
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return ret;
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}
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/* Chained MSI interrupt service routine */
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static void dw_chained_msi_isr(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct pcie_port *pp;
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chained_irq_enter(chip, desc);
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pp = irq_desc_get_handler_data(desc);
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dw_handle_msi_irq(pp);
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chained_irq_exit(chip, desc);
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}
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static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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u64 msi_target;
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msi_target = (u64)pp->msi_data;
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msg->address_lo = lower_32_bits(msi_target);
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msg->address_hi = upper_32_bits(msi_target);
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msg->data = d->hwirq;
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dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
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(int)d->hwirq, msg->address_hi, msg->address_lo);
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}
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static int dw_pci_msi_set_affinity(struct irq_data *d,
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const struct cpumask *mask, bool force)
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{
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return -EINVAL;
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}
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static void dw_pci_bottom_mask(struct irq_data *d)
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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unsigned int res, bit, ctrl;
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unsigned long flags;
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raw_spin_lock_irqsave(&pp->lock, flags);
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ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
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res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
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bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
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pp->irq_mask[ctrl] |= BIT(bit);
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dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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}
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static void dw_pci_bottom_unmask(struct irq_data *d)
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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unsigned int res, bit, ctrl;
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unsigned long flags;
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raw_spin_lock_irqsave(&pp->lock, flags);
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ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
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res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
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bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
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pp->irq_mask[ctrl] &= ~BIT(bit);
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dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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}
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static void dw_pci_bottom_ack(struct irq_data *d)
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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unsigned int res, bit, ctrl;
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ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
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res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
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bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
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dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));
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}
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static struct irq_chip dw_pci_msi_bottom_irq_chip = {
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.name = "DWPCI-MSI",
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.irq_ack = dw_pci_bottom_ack,
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.irq_compose_msi_msg = dw_pci_setup_msi_msg,
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.irq_set_affinity = dw_pci_msi_set_affinity,
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.irq_mask = dw_pci_bottom_mask,
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.irq_unmask = dw_pci_bottom_unmask,
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};
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static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs,
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void *args)
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{
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struct pcie_port *pp = domain->host_data;
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unsigned long flags;
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u32 i;
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int bit;
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raw_spin_lock_irqsave(&pp->lock, flags);
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bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
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order_base_2(nr_irqs));
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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if (bit < 0)
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return -ENOSPC;
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_info(domain, virq + i, bit + i,
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pp->msi_irq_chip,
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pp, handle_edge_irq,
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NULL, NULL);
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return 0;
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}
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static void dw_pcie_irq_domain_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct pcie_port *pp = domain->host_data;
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unsigned long flags;
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raw_spin_lock_irqsave(&pp->lock, flags);
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bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
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order_base_2(nr_irqs));
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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}
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static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
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.alloc = dw_pcie_irq_domain_alloc,
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.free = dw_pcie_irq_domain_free,
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};
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int dw_pcie_allocate_domains(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
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pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
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&dw_pcie_msi_domain_ops, pp);
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if (!pp->irq_domain) {
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dev_err(pci->dev, "Failed to create IRQ domain\n");
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return -ENOMEM;
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}
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irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS);
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pp->msi_domain = pci_msi_create_irq_domain(fwnode,
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&dw_pcie_msi_domain_info,
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pp->irq_domain);
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if (!pp->msi_domain) {
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dev_err(pci->dev, "Failed to create MSI domain\n");
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irq_domain_remove(pp->irq_domain);
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return -ENOMEM;
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}
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return 0;
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}
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static void dw_pcie_free_msi(struct pcie_port *pp)
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{
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if (pp->msi_irq)
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irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL);
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irq_domain_remove(pp->msi_domain);
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irq_domain_remove(pp->irq_domain);
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if (pp->msi_data) {
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct device *dev = pci->dev;
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dma_unmap_single_attrs(dev, pp->msi_data, sizeof(pp->msi_msg),
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DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
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}
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}
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static void dw_pcie_msi_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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u64 msi_target = (u64)pp->msi_data;
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if (!pci_msi_enabled() || !pp->has_msi_ctrl)
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return;
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/* Program the msi_data */
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dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
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dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
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}
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int dw_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct device *dev = pci->dev;
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struct device_node *np = dev->of_node;
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struct platform_device *pdev = to_platform_device(dev);
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struct resource_entry *win;
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struct pci_host_bridge *bridge;
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struct resource *cfg_res;
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int ret;
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raw_spin_lock_init(&pci->pp.lock);
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cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
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if (cfg_res) {
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pp->cfg0_size = resource_size(cfg_res);
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pp->cfg0_base = cfg_res->start;
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pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, cfg_res);
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if (IS_ERR(pp->va_cfg0_base))
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return PTR_ERR(pp->va_cfg0_base);
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} else {
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dev_err(dev, "Missing *config* reg space\n");
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return -ENODEV;
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}
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if (!pci->dbi_base) {
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struct resource *dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
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pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res);
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if (IS_ERR(pci->dbi_base))
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return PTR_ERR(pci->dbi_base);
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}
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bridge = devm_pci_alloc_host_bridge(dev, 0);
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if (!bridge)
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return -ENOMEM;
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pp->bridge = bridge;
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/* Get the I/O range from DT */
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win = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
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if (win) {
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pp->io_size = resource_size(win->res);
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pp->io_bus_addr = win->res->start - win->offset;
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pp->io_base = pci_pio_to_address(win->res->start);
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}
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if (pci->link_gen < 1)
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pci->link_gen = of_pci_get_max_link_speed(np);
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/* Set default bus ops */
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bridge->ops = &dw_pcie_ops;
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bridge->child_ops = &dw_child_pcie_ops;
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if (pp->ops->host_init) {
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ret = pp->ops->host_init(pp);
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if (ret)
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return ret;
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}
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if (pci_msi_enabled()) {
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pp->has_msi_ctrl = !(pp->ops->msi_host_init ||
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of_property_read_bool(np, "msi-parent") ||
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of_property_read_bool(np, "msi-map"));
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if (!pp->num_vectors) {
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pp->num_vectors = MSI_DEF_NUM_VECTORS;
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} else if (pp->num_vectors > MAX_MSI_IRQS) {
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dev_err(dev, "Invalid number of vectors\n");
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return -EINVAL;
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}
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if (pp->ops->msi_host_init) {
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ret = pp->ops->msi_host_init(pp);
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if (ret < 0)
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return ret;
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} else if (pp->has_msi_ctrl) {
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u32 ctrl, num_ctrls;
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num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
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for (ctrl = 0; ctrl < num_ctrls; ctrl++)
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pp->irq_mask[ctrl] = ~0;
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if (!pp->msi_irq) {
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pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi");
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if (pp->msi_irq < 0) {
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pp->msi_irq = platform_get_irq(pdev, 0);
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if (pp->msi_irq < 0)
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return pp->msi_irq;
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}
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}
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pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
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ret = dw_pcie_allocate_domains(pp);
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if (ret)
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return ret;
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if (pp->msi_irq > 0)
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irq_set_chained_handler_and_data(pp->msi_irq,
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dw_chained_msi_isr,
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pp);
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ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
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if (ret)
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dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
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pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg,
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sizeof(pp->msi_msg),
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DMA_FROM_DEVICE,
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DMA_ATTR_SKIP_CPU_SYNC);
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ret = dma_mapping_error(pci->dev, pp->msi_data);
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if (ret) {
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dev_err(pci->dev, "Failed to map MSI data\n");
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pp->msi_data = 0;
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goto err_free_msi;
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}
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}
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}
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dw_pcie_iatu_detect(pci);
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dw_pcie_setup_rc(pp);
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if (!dw_pcie_link_up(pci) && pci->ops && pci->ops->start_link) {
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ret = pci->ops->start_link(pci);
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if (ret)
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goto err_free_msi;
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}
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/* Ignore errors, the link may come up later */
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dw_pcie_wait_for_link(pci);
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bridge->sysdata = pp;
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ret = pci_host_probe(bridge);
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if (!ret)
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return 0;
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err_free_msi:
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if (pp->has_msi_ctrl)
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dw_pcie_free_msi(pp);
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return ret;
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}
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EXPORT_SYMBOL_GPL(dw_pcie_host_init);
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void dw_pcie_host_deinit(struct pcie_port *pp)
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{
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pci_stop_root_bus(pp->bridge->bus);
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pci_remove_root_bus(pp->bridge->bus);
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if (pp->has_msi_ctrl)
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dw_pcie_free_msi(pp);
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}
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EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
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static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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int type;
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u32 busdev;
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struct pcie_port *pp = bus->sysdata;
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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/*
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* Checking whether the link is up here is a last line of defense
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* against platforms that forward errors on the system bus as
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* SError upon PCI configuration transactions issued when the link
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* is down. This check is racy by definition and does not stop
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* the system from triggering an SError if the link goes down
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* after this check is performed.
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*/
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if (!dw_pcie_link_up(pci))
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return NULL;
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busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
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PCIE_ATU_FUNC(PCI_FUNC(devfn));
|
|
|
|
if (pci_is_root_bus(bus->parent))
|
|
type = PCIE_ATU_TYPE_CFG0;
|
|
else
|
|
type = PCIE_ATU_TYPE_CFG1;
|
|
|
|
|
|
dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev, pp->cfg0_size);
|
|
|
|
return pp->va_cfg0_base + where;
|
|
}
|
|
|
|
static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
|
|
int where, int size, u32 *val)
|
|
{
|
|
int ret;
|
|
struct pcie_port *pp = bus->sysdata;
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
|
|
|
ret = pci_generic_config_read(bus, devfn, where, size, val);
|
|
|
|
if (!ret && pci->io_cfg_atu_shared)
|
|
dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
|
|
pp->io_bus_addr, pp->io_size);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
|
|
int where, int size, u32 val)
|
|
{
|
|
int ret;
|
|
struct pcie_port *pp = bus->sysdata;
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
|
|
|
ret = pci_generic_config_write(bus, devfn, where, size, val);
|
|
|
|
if (!ret && pci->io_cfg_atu_shared)
|
|
dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
|
|
pp->io_bus_addr, pp->io_size);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct pci_ops dw_child_pcie_ops = {
|
|
.map_bus = dw_pcie_other_conf_map_bus,
|
|
.read = dw_pcie_rd_other_conf,
|
|
.write = dw_pcie_wr_other_conf,
|
|
};
|
|
|
|
void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
|
|
{
|
|
struct pcie_port *pp = bus->sysdata;
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
|
|
|
if (PCI_SLOT(devfn) > 0)
|
|
return NULL;
|
|
|
|
return pci->dbi_base + where;
|
|
}
|
|
EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus);
|
|
|
|
static struct pci_ops dw_pcie_ops = {
|
|
.map_bus = dw_pcie_own_conf_map_bus,
|
|
.read = pci_generic_config_read,
|
|
.write = pci_generic_config_write,
|
|
};
|
|
|
|
void dw_pcie_setup_rc(struct pcie_port *pp)
|
|
{
|
|
int i;
|
|
u32 val, ctrl, num_ctrls;
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
|
|
|
/*
|
|
* Enable DBI read-only registers for writing/updating configuration.
|
|
* Write permission gets disabled towards the end of this function.
|
|
*/
|
|
dw_pcie_dbi_ro_wr_en(pci);
|
|
|
|
dw_pcie_setup(pci);
|
|
|
|
if (pp->has_msi_ctrl) {
|
|
num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
|
|
|
|
/* Initialize IRQ Status array */
|
|
for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
|
|
dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
|
|
(ctrl * MSI_REG_CTRL_BLOCK_SIZE),
|
|
pp->irq_mask[ctrl]);
|
|
dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
|
|
(ctrl * MSI_REG_CTRL_BLOCK_SIZE),
|
|
~0);
|
|
}
|
|
}
|
|
|
|
dw_pcie_msi_init(pp);
|
|
|
|
/* Setup RC BARs */
|
|
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
|
|
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
|
|
|
|
/* Setup interrupt pins */
|
|
val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
|
|
val &= 0xffff00ff;
|
|
val |= 0x00000100;
|
|
dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
|
|
|
|
/* Setup bus numbers */
|
|
val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
|
|
val &= 0xff000000;
|
|
val |= 0x00ff0100;
|
|
dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
|
|
|
|
/* Setup command register */
|
|
val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
|
|
val &= 0xffff0000;
|
|
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
|
|
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
|
|
dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
|
|
|
|
/* Ensure all outbound windows are disabled so there are multiple matches */
|
|
for (i = 0; i < pci->num_ob_windows; i++)
|
|
dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND);
|
|
|
|
/*
|
|
* If the platform provides its own child bus config accesses, it means
|
|
* the platform uses its own address translation component rather than
|
|
* ATU, so we should not program the ATU here.
|
|
*/
|
|
if (pp->bridge->child_ops == &dw_child_pcie_ops) {
|
|
int atu_idx = 0;
|
|
struct resource_entry *entry;
|
|
|
|
/* Get last memory resource entry */
|
|
resource_list_for_each_entry(entry, &pp->bridge->windows) {
|
|
if (resource_type(entry->res) != IORESOURCE_MEM)
|
|
continue;
|
|
|
|
if (pci->num_ob_windows <= ++atu_idx)
|
|
break;
|
|
|
|
dw_pcie_prog_outbound_atu(pci, atu_idx,
|
|
PCIE_ATU_TYPE_MEM, entry->res->start,
|
|
entry->res->start - entry->offset,
|
|
resource_size(entry->res));
|
|
}
|
|
|
|
if (pp->io_size) {
|
|
if (pci->num_ob_windows > ++atu_idx)
|
|
dw_pcie_prog_outbound_atu(pci, atu_idx,
|
|
PCIE_ATU_TYPE_IO, pp->io_base,
|
|
pp->io_bus_addr, pp->io_size);
|
|
else
|
|
pci->io_cfg_atu_shared = true;
|
|
}
|
|
|
|
if (pci->num_ob_windows <= atu_idx)
|
|
dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)",
|
|
pci->num_ob_windows);
|
|
}
|
|
|
|
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
|
|
|
|
/* Program correct class for RC */
|
|
dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
|
|
|
|
val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
|
|
val |= PORT_LOGIC_SPEED_CHANGE;
|
|
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
|
|
|
|
dw_pcie_dbi_ro_wr_dis(pci);
|
|
}
|
|
EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
|