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![Peter Geis](/assets/img/avatar_default.png)
The legacy interrupts on the rk356x PCIe controller are handled by a single muxed interrupt. Add IRQ domain support to the pcie-dw-rockchip driver to support the virtual domain. Link: https://lore.kernel.org/r/20220429123832.2376381-4-pgwipeout@gmail.com Signed-off-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Marc Zyngier <maz@kernel.org>
368 lines
9.5 KiB
C
368 lines
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for Rockchip SoCs.
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*
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* Copyright (C) 2021 Rockchip Electronics Co., Ltd.
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* http://www.rock-chips.com
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*
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* Author: Simon Xue <xxm@rock-chips.com>
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*/
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#include <linux/clk.h>
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#include <linux/gpio/consumer.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "pcie-designware.h"
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/*
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* The upper 16 bits of PCIE_CLIENT_CONFIG are a write
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* mask for the lower 16 bits.
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*/
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#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
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#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
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#define HIWORD_DISABLE_BIT(val) HIWORD_UPDATE(val, ~val)
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#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
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#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40)
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#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc)
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#define PCIE_SMLH_LINKUP BIT(16)
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#define PCIE_RDLH_LINKUP BIT(17)
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#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
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#define PCIE_L0S_ENTRY 0x11
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#define PCIE_CLIENT_GENERAL_CONTROL 0x0
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#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
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#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c
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#define PCIE_CLIENT_GENERAL_DEBUG 0x104
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#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
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#define PCIE_CLIENT_LTSSM_STATUS 0x300
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#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
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#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
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struct rockchip_pcie {
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struct dw_pcie pci;
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void __iomem *apb_base;
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struct phy *phy;
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struct clk_bulk_data *clks;
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unsigned int clk_cnt;
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struct reset_control *rst;
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struct gpio_desc *rst_gpio;
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struct regulator *vpcie3v3;
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struct irq_domain *irq_domain;
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};
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static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip,
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u32 reg)
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{
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return readl_relaxed(rockchip->apb_base + reg);
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}
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static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip,
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u32 val, u32 reg)
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{
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writel_relaxed(val, rockchip->apb_base + reg);
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}
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static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
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unsigned long reg, hwirq;
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chained_irq_enter(chip, desc);
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reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY);
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for_each_set_bit(hwirq, ®, 4)
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generic_handle_domain_irq(rockchip->irq_domain, hwirq);
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chained_irq_exit(chip, desc);
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}
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static void rockchip_intx_mask(struct irq_data *data)
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{
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rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
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HIWORD_UPDATE_BIT(BIT(data->hwirq)),
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PCIE_CLIENT_INTR_MASK_LEGACY);
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};
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static void rockchip_intx_unmask(struct irq_data *data)
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{
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rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
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HIWORD_DISABLE_BIT(BIT(data->hwirq)),
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PCIE_CLIENT_INTR_MASK_LEGACY);
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};
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static struct irq_chip rockchip_intx_irq_chip = {
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.name = "INTx",
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.irq_mask = rockchip_intx_mask,
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.irq_unmask = rockchip_intx_unmask,
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.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
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};
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static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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}
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static const struct irq_domain_ops intx_domain_ops = {
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.map = rockchip_pcie_intx_map,
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};
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static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
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{
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struct device *dev = rockchip->pci.dev;
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struct device_node *intc;
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intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller");
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if (!intc) {
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dev_err(dev, "missing child interrupt-controller node\n");
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return -EINVAL;
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}
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rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
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&intx_domain_ops, rockchip);
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of_node_put(intc);
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if (!rockchip->irq_domain) {
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dev_err(dev, "failed to get a INTx IRQ domain\n");
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return -EINVAL;
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}
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return 0;
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}
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static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
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{
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rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
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PCIE_CLIENT_GENERAL_CONTROL);
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}
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static int rockchip_pcie_link_up(struct dw_pcie *pci)
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{
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struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
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u32 val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS);
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if ((val & PCIE_LINKUP) == PCIE_LINKUP &&
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(val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY)
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return 1;
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return 0;
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}
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static int rockchip_pcie_start_link(struct dw_pcie *pci)
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{
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struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
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/* Reset device */
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gpiod_set_value_cansleep(rockchip->rst_gpio, 0);
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rockchip_pcie_enable_ltssm(rockchip);
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/*
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* PCIe requires the refclk to be stable for 100µs prior to releasing
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* PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI
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* Express Card Electromechanical Specification, 1.1. However, we don't
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* know if the refclk is coming from RC's PHY or external OSC. If it's
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* from RC, so enabling LTSSM is the just right place to release #PERST.
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* We need more extra time as before, rather than setting just
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* 100us as we don't know how long should the device need to reset.
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*/
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msleep(100);
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gpiod_set_value_cansleep(rockchip->rst_gpio, 1);
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return 0;
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}
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static int rockchip_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
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struct device *dev = rockchip->pci.dev;
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u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
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int irq, ret;
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irq = of_irq_get_byname(dev->of_node, "legacy");
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if (irq < 0)
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return irq;
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ret = rockchip_pcie_init_irq_domain(rockchip);
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if (ret < 0)
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dev_err(dev, "failed to init irq domain\n");
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irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler,
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rockchip);
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/* LTSSM enable control mode */
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rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
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rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE,
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PCIE_CLIENT_GENERAL_CONTROL);
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return 0;
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}
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static const struct dw_pcie_host_ops rockchip_pcie_host_ops = {
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.host_init = rockchip_pcie_host_init,
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};
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static int rockchip_pcie_clk_init(struct rockchip_pcie *rockchip)
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{
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struct device *dev = rockchip->pci.dev;
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int ret;
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ret = devm_clk_bulk_get_all(dev, &rockchip->clks);
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if (ret < 0)
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return ret;
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rockchip->clk_cnt = ret;
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return clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks);
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}
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static int rockchip_pcie_resource_get(struct platform_device *pdev,
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struct rockchip_pcie *rockchip)
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{
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rockchip->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");
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if (IS_ERR(rockchip->apb_base))
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return PTR_ERR(rockchip->apb_base);
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rockchip->rst_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
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GPIOD_OUT_HIGH);
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if (IS_ERR(rockchip->rst_gpio))
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return PTR_ERR(rockchip->rst_gpio);
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rockchip->rst = devm_reset_control_array_get_exclusive(&pdev->dev);
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if (IS_ERR(rockchip->rst))
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return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst),
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"failed to get reset lines\n");
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return 0;
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}
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static int rockchip_pcie_phy_init(struct rockchip_pcie *rockchip)
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{
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struct device *dev = rockchip->pci.dev;
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int ret;
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rockchip->phy = devm_phy_get(dev, "pcie-phy");
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if (IS_ERR(rockchip->phy))
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return dev_err_probe(dev, PTR_ERR(rockchip->phy),
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"missing PHY\n");
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ret = phy_init(rockchip->phy);
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if (ret < 0)
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return ret;
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ret = phy_power_on(rockchip->phy);
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if (ret)
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phy_exit(rockchip->phy);
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return ret;
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}
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static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip)
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{
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phy_exit(rockchip->phy);
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phy_power_off(rockchip->phy);
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}
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static const struct dw_pcie_ops dw_pcie_ops = {
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.link_up = rockchip_pcie_link_up,
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.start_link = rockchip_pcie_start_link,
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};
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static int rockchip_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rockchip_pcie *rockchip;
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struct pcie_port *pp;
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int ret;
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rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
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if (!rockchip)
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return -ENOMEM;
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platform_set_drvdata(pdev, rockchip);
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rockchip->pci.dev = dev;
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rockchip->pci.ops = &dw_pcie_ops;
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pp = &rockchip->pci.pp;
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pp->ops = &rockchip_pcie_host_ops;
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ret = rockchip_pcie_resource_get(pdev, rockchip);
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if (ret)
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return ret;
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ret = reset_control_assert(rockchip->rst);
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if (ret)
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return ret;
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/* DON'T MOVE ME: must be enable before PHY init */
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rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
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if (IS_ERR(rockchip->vpcie3v3)) {
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if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)
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return dev_err_probe(dev, PTR_ERR(rockchip->vpcie3v3),
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"failed to get vpcie3v3 regulator\n");
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rockchip->vpcie3v3 = NULL;
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} else {
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ret = regulator_enable(rockchip->vpcie3v3);
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if (ret) {
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dev_err(dev, "failed to enable vpcie3v3 regulator\n");
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return ret;
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}
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}
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ret = rockchip_pcie_phy_init(rockchip);
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if (ret)
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goto disable_regulator;
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ret = reset_control_deassert(rockchip->rst);
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if (ret)
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goto deinit_phy;
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ret = rockchip_pcie_clk_init(rockchip);
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if (ret)
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goto deinit_phy;
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ret = dw_pcie_host_init(pp);
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if (!ret)
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return 0;
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clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);
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deinit_phy:
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rockchip_pcie_phy_deinit(rockchip);
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disable_regulator:
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if (rockchip->vpcie3v3)
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regulator_disable(rockchip->vpcie3v3);
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return ret;
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}
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static const struct of_device_id rockchip_pcie_of_match[] = {
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{ .compatible = "rockchip,rk3568-pcie", },
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{},
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};
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static struct platform_driver rockchip_pcie_driver = {
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.driver = {
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.name = "rockchip-dw-pcie",
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.of_match_table = rockchip_pcie_of_match,
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.suppress_bind_attrs = true,
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},
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.probe = rockchip_pcie_probe,
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};
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builtin_platform_driver(rockchip_pcie_driver);
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