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![Fan Fei](/assets/img/avatar_default.png)
Rename struct intel_pcie_port to intel_pcie to match the convention of <driver>_pcie. No functional change intended. Link: https://lore.kernel.org/r/20211223011054.1227810-11-helgaas@kernel.org Signed-off-by: Fan Fei <ffclaire1224@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Rahul Tanwar <rtanwar@maxlinear.com>
463 lines
11 KiB
C
463 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for Intel Gateway SoCs
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*
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* Copyright (c) 2019 Intel Corporation.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/gpio/consumer.h>
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#include <linux/iopoll.h>
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#include <linux/pci_regs.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include "../../pci.h"
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#include "pcie-designware.h"
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#define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
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#define PORT_AFR_N_FTS_GEN3 180
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#define PORT_AFR_N_FTS_GEN4 196
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/* PCIe Application logic Registers */
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#define PCIE_APP_CCR 0x10
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#define PCIE_APP_CCR_LTSSM_ENABLE BIT(0)
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#define PCIE_APP_MSG_CR 0x30
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#define PCIE_APP_MSG_XMT_PM_TURNOFF BIT(0)
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#define PCIE_APP_PMC 0x44
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#define PCIE_APP_PMC_IN_L2 BIT(20)
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#define PCIE_APP_IRNEN 0xF4
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#define PCIE_APP_IRNCR 0xF8
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#define PCIE_APP_IRN_AER_REPORT BIT(0)
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#define PCIE_APP_IRN_PME BIT(2)
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#define PCIE_APP_IRN_RX_VDM_MSG BIT(4)
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#define PCIE_APP_IRN_PM_TO_ACK BIT(9)
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#define PCIE_APP_IRN_LINK_AUTO_BW_STAT BIT(11)
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#define PCIE_APP_IRN_BW_MGT BIT(12)
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#define PCIE_APP_IRN_INTA BIT(13)
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#define PCIE_APP_IRN_INTB BIT(14)
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#define PCIE_APP_IRN_INTC BIT(15)
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#define PCIE_APP_IRN_INTD BIT(16)
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#define PCIE_APP_IRN_MSG_LTR BIT(18)
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#define PCIE_APP_IRN_SYS_ERR_RC BIT(29)
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#define PCIE_APP_INTX_OFST 12
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#define PCIE_APP_IRN_INT \
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(PCIE_APP_IRN_AER_REPORT | PCIE_APP_IRN_PME | \
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PCIE_APP_IRN_RX_VDM_MSG | PCIE_APP_IRN_SYS_ERR_RC | \
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PCIE_APP_IRN_PM_TO_ACK | PCIE_APP_IRN_MSG_LTR | \
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PCIE_APP_IRN_BW_MGT | PCIE_APP_IRN_LINK_AUTO_BW_STAT | \
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PCIE_APP_IRN_INTA | PCIE_APP_IRN_INTB | \
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PCIE_APP_IRN_INTC | PCIE_APP_IRN_INTD)
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#define BUS_IATU_OFFSET SZ_256M
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#define RESET_INTERVAL_MS 100
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struct intel_pcie_soc {
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unsigned int pcie_ver;
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};
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struct intel_pcie {
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struct dw_pcie pci;
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void __iomem *app_base;
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struct gpio_desc *reset_gpio;
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u32 rst_intrvl;
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struct clk *core_clk;
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struct reset_control *core_rst;
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struct phy *phy;
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};
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static void pcie_update_bits(void __iomem *base, u32 ofs, u32 mask, u32 val)
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{
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u32 old;
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old = readl(base + ofs);
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val = (old & ~mask) | (val & mask);
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if (val != old)
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writel(val, base + ofs);
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}
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static inline void pcie_app_wr(struct intel_pcie *pcie, u32 ofs, u32 val)
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{
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writel(val, pcie->app_base + ofs);
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}
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static void pcie_app_wr_mask(struct intel_pcie *pcie, u32 ofs,
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u32 mask, u32 val)
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{
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pcie_update_bits(pcie->app_base, ofs, mask, val);
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}
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static inline u32 pcie_rc_cfg_rd(struct intel_pcie *pcie, u32 ofs)
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{
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return dw_pcie_readl_dbi(&pcie->pci, ofs);
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}
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static inline void pcie_rc_cfg_wr(struct intel_pcie *pcie, u32 ofs, u32 val)
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{
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dw_pcie_writel_dbi(&pcie->pci, ofs, val);
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}
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static void pcie_rc_cfg_wr_mask(struct intel_pcie *pcie, u32 ofs,
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u32 mask, u32 val)
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{
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pcie_update_bits(pcie->pci.dbi_base, ofs, mask, val);
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}
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static void intel_pcie_ltssm_enable(struct intel_pcie *pcie)
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{
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pcie_app_wr_mask(pcie, PCIE_APP_CCR, PCIE_APP_CCR_LTSSM_ENABLE,
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PCIE_APP_CCR_LTSSM_ENABLE);
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}
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static void intel_pcie_ltssm_disable(struct intel_pcie *pcie)
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{
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pcie_app_wr_mask(pcie, PCIE_APP_CCR, PCIE_APP_CCR_LTSSM_ENABLE, 0);
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}
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static void intel_pcie_link_setup(struct intel_pcie *pcie)
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{
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u32 val;
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u8 offset = dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP);
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val = pcie_rc_cfg_rd(pcie, offset + PCI_EXP_LNKCTL);
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val &= ~(PCI_EXP_LNKCTL_LD | PCI_EXP_LNKCTL_ASPMC);
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pcie_rc_cfg_wr(pcie, offset + PCI_EXP_LNKCTL, val);
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}
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static void intel_pcie_init_n_fts(struct dw_pcie *pci)
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{
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switch (pci->link_gen) {
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case 3:
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pci->n_fts[1] = PORT_AFR_N_FTS_GEN3;
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break;
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case 4:
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pci->n_fts[1] = PORT_AFR_N_FTS_GEN4;
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break;
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default:
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pci->n_fts[1] = PORT_AFR_N_FTS_GEN12_DFT;
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break;
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}
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pci->n_fts[0] = PORT_AFR_N_FTS_GEN12_DFT;
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}
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static int intel_pcie_ep_rst_init(struct intel_pcie *pcie)
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{
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struct device *dev = pcie->pci.dev;
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int ret;
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pcie->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
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if (IS_ERR(pcie->reset_gpio)) {
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ret = PTR_ERR(pcie->reset_gpio);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "Failed to request PCIe GPIO: %d\n", ret);
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return ret;
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}
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/* Make initial reset last for 100us */
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usleep_range(100, 200);
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return 0;
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}
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static void intel_pcie_core_rst_assert(struct intel_pcie *pcie)
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{
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reset_control_assert(pcie->core_rst);
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}
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static void intel_pcie_core_rst_deassert(struct intel_pcie *pcie)
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{
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/*
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* One micro-second delay to make sure the reset pulse
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* wide enough so that core reset is clean.
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*/
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udelay(1);
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reset_control_deassert(pcie->core_rst);
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/*
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* Some SoC core reset also reset PHY, more delay needed
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* to make sure the reset process is done.
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*/
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usleep_range(1000, 2000);
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}
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static void intel_pcie_device_rst_assert(struct intel_pcie *pcie)
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{
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gpiod_set_value_cansleep(pcie->reset_gpio, 1);
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}
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static void intel_pcie_device_rst_deassert(struct intel_pcie *pcie)
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{
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msleep(pcie->rst_intrvl);
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gpiod_set_value_cansleep(pcie->reset_gpio, 0);
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}
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static void intel_pcie_core_irq_disable(struct intel_pcie *pcie)
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{
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pcie_app_wr(pcie, PCIE_APP_IRNEN, 0);
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pcie_app_wr(pcie, PCIE_APP_IRNCR, PCIE_APP_IRN_INT);
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}
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static int intel_pcie_get_resources(struct platform_device *pdev)
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{
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struct intel_pcie *pcie = platform_get_drvdata(pdev);
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struct dw_pcie *pci = &pcie->pci;
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struct device *dev = pci->dev;
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int ret;
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pcie->core_clk = devm_clk_get(dev, NULL);
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if (IS_ERR(pcie->core_clk)) {
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ret = PTR_ERR(pcie->core_clk);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "Failed to get clks: %d\n", ret);
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return ret;
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}
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pcie->core_rst = devm_reset_control_get(dev, NULL);
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if (IS_ERR(pcie->core_rst)) {
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ret = PTR_ERR(pcie->core_rst);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "Failed to get resets: %d\n", ret);
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return ret;
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}
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ret = device_property_read_u32(dev, "reset-assert-ms",
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&pcie->rst_intrvl);
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if (ret)
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pcie->rst_intrvl = RESET_INTERVAL_MS;
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pcie->app_base = devm_platform_ioremap_resource_byname(pdev, "app");
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if (IS_ERR(pcie->app_base))
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return PTR_ERR(pcie->app_base);
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pcie->phy = devm_phy_get(dev, "pcie");
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if (IS_ERR(pcie->phy)) {
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ret = PTR_ERR(pcie->phy);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "Couldn't get pcie-phy: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int intel_pcie_wait_l2(struct intel_pcie *pcie)
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{
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u32 value;
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int ret;
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struct dw_pcie *pci = &pcie->pci;
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if (pci->link_gen < 3)
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return 0;
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/* Send PME_TURN_OFF message */
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pcie_app_wr_mask(pcie, PCIE_APP_MSG_CR, PCIE_APP_MSG_XMT_PM_TURNOFF,
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PCIE_APP_MSG_XMT_PM_TURNOFF);
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/* Read PMC status and wait for falling into L2 link state */
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ret = readl_poll_timeout(pcie->app_base + PCIE_APP_PMC, value,
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value & PCIE_APP_PMC_IN_L2, 20,
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jiffies_to_usecs(5 * HZ));
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if (ret)
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dev_err(pcie->pci.dev, "PCIe link enter L2 timeout!\n");
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return ret;
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}
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static void intel_pcie_turn_off(struct intel_pcie *pcie)
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{
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if (dw_pcie_link_up(&pcie->pci))
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intel_pcie_wait_l2(pcie);
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/* Put endpoint device in reset state */
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intel_pcie_device_rst_assert(pcie);
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pcie_rc_cfg_wr_mask(pcie, PCI_COMMAND, PCI_COMMAND_MEMORY, 0);
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}
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static int intel_pcie_host_setup(struct intel_pcie *pcie)
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{
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int ret;
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struct dw_pcie *pci = &pcie->pci;
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intel_pcie_core_rst_assert(pcie);
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intel_pcie_device_rst_assert(pcie);
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ret = phy_init(pcie->phy);
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if (ret)
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return ret;
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intel_pcie_core_rst_deassert(pcie);
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ret = clk_prepare_enable(pcie->core_clk);
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if (ret) {
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dev_err(pcie->pci.dev, "Core clock enable failed: %d\n", ret);
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goto clk_err;
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}
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pci->atu_base = pci->dbi_base + 0xC0000;
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intel_pcie_ltssm_disable(pcie);
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intel_pcie_link_setup(pcie);
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intel_pcie_init_n_fts(pci);
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dw_pcie_setup_rc(&pci->pp);
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dw_pcie_upconfig_setup(pci);
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intel_pcie_device_rst_deassert(pcie);
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intel_pcie_ltssm_enable(pcie);
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ret = dw_pcie_wait_for_link(pci);
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if (ret)
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goto app_init_err;
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/* Enable integrated interrupts */
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pcie_app_wr_mask(pcie, PCIE_APP_IRNEN, PCIE_APP_IRN_INT,
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PCIE_APP_IRN_INT);
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return 0;
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app_init_err:
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clk_disable_unprepare(pcie->core_clk);
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clk_err:
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intel_pcie_core_rst_assert(pcie);
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phy_exit(pcie->phy);
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return ret;
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}
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static void __intel_pcie_remove(struct intel_pcie *pcie)
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{
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intel_pcie_core_irq_disable(pcie);
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intel_pcie_turn_off(pcie);
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clk_disable_unprepare(pcie->core_clk);
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intel_pcie_core_rst_assert(pcie);
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phy_exit(pcie->phy);
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}
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static int intel_pcie_remove(struct platform_device *pdev)
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{
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struct intel_pcie *pcie = platform_get_drvdata(pdev);
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struct pcie_port *pp = &pcie->pci.pp;
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dw_pcie_host_deinit(pp);
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__intel_pcie_remove(pcie);
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return 0;
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}
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static int __maybe_unused intel_pcie_suspend_noirq(struct device *dev)
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{
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struct intel_pcie *pcie = dev_get_drvdata(dev);
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int ret;
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intel_pcie_core_irq_disable(pcie);
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ret = intel_pcie_wait_l2(pcie);
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if (ret)
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return ret;
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phy_exit(pcie->phy);
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clk_disable_unprepare(pcie->core_clk);
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return ret;
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}
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static int __maybe_unused intel_pcie_resume_noirq(struct device *dev)
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{
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struct intel_pcie *pcie = dev_get_drvdata(dev);
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return intel_pcie_host_setup(pcie);
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}
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static int intel_pcie_rc_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct intel_pcie *pcie = dev_get_drvdata(pci->dev);
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return intel_pcie_host_setup(pcie);
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}
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static u64 intel_pcie_cpu_addr(struct dw_pcie *pcie, u64 cpu_addr)
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{
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return cpu_addr + BUS_IATU_OFFSET;
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}
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static const struct dw_pcie_ops intel_pcie_ops = {
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.cpu_addr_fixup = intel_pcie_cpu_addr,
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};
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static const struct dw_pcie_host_ops intel_pcie_dw_ops = {
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.host_init = intel_pcie_rc_init,
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};
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static const struct intel_pcie_soc pcie_data = {
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.pcie_ver = 0x520A,
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};
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static int intel_pcie_probe(struct platform_device *pdev)
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{
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const struct intel_pcie_soc *data;
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struct device *dev = &pdev->dev;
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struct intel_pcie *pcie;
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struct pcie_port *pp;
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struct dw_pcie *pci;
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int ret;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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platform_set_drvdata(pdev, pcie);
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pci = &pcie->pci;
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pci->dev = dev;
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pp = &pci->pp;
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ret = intel_pcie_get_resources(pdev);
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if (ret)
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return ret;
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ret = intel_pcie_ep_rst_init(pcie);
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if (ret)
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return ret;
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data = device_get_match_data(dev);
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if (!data)
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return -ENODEV;
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pci->ops = &intel_pcie_ops;
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pci->version = data->pcie_ver;
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pp->ops = &intel_pcie_dw_ops;
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(dev, "Cannot initialize host\n");
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return ret;
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}
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return 0;
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}
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static const struct dev_pm_ops intel_pcie_pm_ops = {
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pcie_suspend_noirq,
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intel_pcie_resume_noirq)
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};
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static const struct of_device_id of_intel_pcie_match[] = {
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{ .compatible = "intel,lgm-pcie", .data = &pcie_data },
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{}
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};
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static struct platform_driver intel_pcie_driver = {
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.probe = intel_pcie_probe,
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.remove = intel_pcie_remove,
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.driver = {
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.name = "intel-gw-pcie",
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.of_match_table = of_intel_pcie_match,
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.pm = &intel_pcie_pm_ops,
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},
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};
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builtin_platform_driver(intel_pcie_driver);
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