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df44bc16e6
To avoid the actual PLL settings to differ from the state expected by the clock driver, the codec should only be fully reset before the clocks are registered. But we also need to ensure that the software reset happens at all before clock registration, as not all boards have a reset GPIO. Move the software reset from aic32x4_component_probe() to aic32x4_probe() and reorder the reset and registration sequence: 1. Reset via GPIO (if available) 2. Reset via software 3. Register component 4. Register clocks Note that aic32x4_component_probe() is only called after aic32x4_probe() has finished, so the reset in aic32x4_component_probe() was happening too late. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Link: https://lore.kernel.org/r/20200902133043.19504-2-matthias.schiffer@ew.tq-group.com Signed-off-by: Mark Brown <broonie@kernel.org> |
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| .. | ||
| ac97 | ||
| aoa | ||
| arm | ||
| atmel | ||
| core | ||
| drivers | ||
| firewire | ||
| hda | ||
| i2c | ||
| isa | ||
| mips | ||
| oss | ||
| parisc | ||
| pci | ||
| pcmcia | ||
| ppc | ||
| sh | ||
| soc | ||
| sparc | ||
| spi | ||
| synth | ||
| usb | ||
| x86 | ||
| xen | ||
| ac97_bus.c | ||
| Kconfig | ||
| last.c | ||
| Makefile | ||
| sound_core.c | ||