谢致邦 (XIE Zhibang) 60bc84e227 MIPS: Loongson: Merge load addresses ... Systems based upon the Loongson 1B & 1C CPUs share the same load address, as do those based upon Loongson 1A. Unify the definition of this load address to reduce duplication & avoid the need for an extra Loongson 1A case in future. [paul.burton@mips.com: Rewrite commit message.] Signed-off-by: 谢致邦 (XIE Zhibang) <Yeking@Red54.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/14927/ Cc: linux-mips@linux-mips.org		2018-07-30 18:59:01 -07:00
..
common	MIPS: loongson1: set default number of rx and tx queues for stmmac	2017-10-09 14:53:38 +02:00
ls1b	MIPS: Loongson1: Add watchdog support for Loongson1 board	2017-01-03 16:34:42 +01:00
ls1c	MIPS: Loongson1: Add watchdog support for Loongson1 board	2017-01-03 16:34:42 +01:00
Kconfig	MIPS: use generic dma noncoherent ops for simple noncoherent platforms	2018-06-24 09:26:05 -07:00
Makefile	MIPS: Loongson1C: Add board support	2016-10-04 16:13:57 +02:00
Platform	MIPS: Loongson: Merge load addresses	2018-07-30 18:59:01 -07:00