mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-29 23:53:32 +00:00
3a0990ca1a
Caching dates is never a good idea ;-)
Fixes: e7affb1dba ("powerpc/cache: add cache flush operation for various e500")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Scott Wood <oss@buserror.net>
342 lines
7 KiB
ArmAsm
342 lines
7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* This file contains low level CPU setup functions.
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* Kumar Gala <galak@kernel.crashing.org>
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* Based on cpu_setup_6xx code by
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* Benjamin Herrenschmidt <benh@kernel.crashing.org>
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*/
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <asm/cputable.h>
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#include <asm/ppc_asm.h>
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#include <asm/nohash/mmu-book3e.h>
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#include <asm/asm-offsets.h>
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#include <asm/mpc85xx.h>
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_GLOBAL(__e500_icache_setup)
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mfspr r0, SPRN_L1CSR1
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andi. r3, r0, L1CSR1_ICE
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bnelr /* Already enabled */
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oris r0, r0, L1CSR1_CPE@h
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ori r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR | L1CSR1_ICE)
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mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */
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isync
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blr
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_GLOBAL(__e500_dcache_setup)
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mfspr r0, SPRN_L1CSR0
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andi. r3, r0, L1CSR0_DCE
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bnelr /* Already enabled */
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msync
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isync
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li r0, 0
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mtspr SPRN_L1CSR0, r0 /* Disable */
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msync
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isync
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li r0, (L1CSR0_DCFI | L1CSR0_CLFC)
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mtspr SPRN_L1CSR0, r0 /* Invalidate */
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isync
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1: mfspr r0, SPRN_L1CSR0
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andi. r3, r0, L1CSR0_CLFC
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bne+ 1b /* Wait for lock bits reset */
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oris r0, r0, L1CSR0_CPE@h
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ori r0, r0, L1CSR0_DCE
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msync
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isync
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mtspr SPRN_L1CSR0, r0 /* Enable */
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isync
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blr
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/*
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* FIXME - we haven't yet done testing to determine a reasonable default
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* value for PW20_WAIT_IDLE_BIT.
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*/
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#define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
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_GLOBAL(setup_pw20_idle)
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mfspr r3, SPRN_PWRMGTCR0
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/* Set PW20_WAIT bit, enable pw20 state*/
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ori r3, r3, PWRMGTCR0_PW20_WAIT
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li r11, PW20_WAIT_IDLE_BIT
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/* Set Automatic PW20 Core Idle Count */
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rlwimi r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT
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mtspr SPRN_PWRMGTCR0, r3
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blr
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/*
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* FIXME - we haven't yet done testing to determine a reasonable default
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* value for AV_WAIT_IDLE_BIT.
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*/
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#define AV_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
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_GLOBAL(setup_altivec_idle)
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mfspr r3, SPRN_PWRMGTCR0
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/* Enable Altivec Idle */
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oris r3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h
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li r11, AV_WAIT_IDLE_BIT
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/* Set Automatic AltiVec Idle Count */
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rlwimi r3, r11, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT
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mtspr SPRN_PWRMGTCR0, r3
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blr
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#ifdef CONFIG_PPC_E500MC
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_GLOBAL(__setup_cpu_e6500)
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mflr r6
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#ifdef CONFIG_PPC64
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bl setup_altivec_ivors
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/* Touch IVOR42 only if the CPU supports E.HV category */
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mfspr r10,SPRN_MMUCFG
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rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
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beq 1f
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bl setup_lrat_ivor
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1:
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#endif
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bl setup_pw20_idle
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bl setup_altivec_idle
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bl __setup_cpu_e5500
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mtlr r6
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blr
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#endif /* CONFIG_PPC_E500MC */
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#ifdef CONFIG_PPC32
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#ifdef CONFIG_E200
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_GLOBAL(__setup_cpu_e200)
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/* enable dedicated debug exception handling resources (Debug APU) */
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mfspr r3,SPRN_HID0
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ori r3,r3,HID0_DAPUEN@l
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mtspr SPRN_HID0,r3
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b __setup_e200_ivors
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#endif /* CONFIG_E200 */
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#ifdef CONFIG_E500
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#ifndef CONFIG_PPC_E500MC
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_GLOBAL(__setup_cpu_e500v1)
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_GLOBAL(__setup_cpu_e500v2)
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mflr r4
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bl __e500_icache_setup
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bl __e500_dcache_setup
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bl __setup_e500_ivors
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#if defined(CONFIG_FSL_RIO) || defined(CONFIG_FSL_PCI)
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/* Ensure that RFXE is set */
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mfspr r3,SPRN_HID1
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oris r3,r3,HID1_RFXE@h
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mtspr SPRN_HID1,r3
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#endif
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mtlr r4
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blr
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#else /* CONFIG_PPC_E500MC */
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_GLOBAL(__setup_cpu_e500mc)
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_GLOBAL(__setup_cpu_e5500)
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mflr r5
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bl __e500_icache_setup
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bl __e500_dcache_setup
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bl __setup_e500mc_ivors
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/*
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* We only want to touch IVOR38-41 if we're running on hardware
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* that supports category E.HV. The architectural way to determine
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* this is MMUCFG[LPIDSIZE].
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*/
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mfspr r3, SPRN_MMUCFG
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rlwinm. r3, r3, 0, MMUCFG_LPIDSIZE
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beq 1f
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bl __setup_ehv_ivors
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b 2f
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1:
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lwz r3, CPU_SPEC_FEATURES(r4)
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/* We need this check as cpu_setup is also called for
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* the secondary cores. So, if we have already cleared
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* the feature on the primary core, avoid doing it on the
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* secondary core.
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*/
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andi. r6, r3, CPU_FTR_EMB_HV
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beq 2f
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rlwinm r3, r3, 0, ~CPU_FTR_EMB_HV
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stw r3, CPU_SPEC_FEATURES(r4)
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2:
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mtlr r5
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blr
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#endif /* CONFIG_PPC_E500MC */
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#endif /* CONFIG_E500 */
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#endif /* CONFIG_PPC32 */
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#ifdef CONFIG_PPC_BOOK3E_64
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_GLOBAL(__restore_cpu_e6500)
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mflr r5
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bl setup_altivec_ivors
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/* Touch IVOR42 only if the CPU supports E.HV category */
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mfspr r10,SPRN_MMUCFG
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rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
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beq 1f
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bl setup_lrat_ivor
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1:
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bl setup_pw20_idle
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bl setup_altivec_idle
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bl __restore_cpu_e5500
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mtlr r5
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blr
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_GLOBAL(__restore_cpu_e5500)
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mflr r4
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bl __e500_icache_setup
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bl __e500_dcache_setup
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bl __setup_base_ivors
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bl setup_perfmon_ivor
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bl setup_doorbell_ivors
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/*
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* We only want to touch IVOR38-41 if we're running on hardware
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* that supports category E.HV. The architectural way to determine
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* this is MMUCFG[LPIDSIZE].
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*/
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mfspr r10,SPRN_MMUCFG
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rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
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beq 1f
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bl setup_ehv_ivors
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1:
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mtlr r4
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blr
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_GLOBAL(__setup_cpu_e5500)
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mflr r5
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bl __e500_icache_setup
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bl __e500_dcache_setup
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bl __setup_base_ivors
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bl setup_perfmon_ivor
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bl setup_doorbell_ivors
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/*
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* We only want to touch IVOR38-41 if we're running on hardware
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* that supports category E.HV. The architectural way to determine
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* this is MMUCFG[LPIDSIZE].
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*/
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mfspr r10,SPRN_MMUCFG
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rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
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beq 1f
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bl setup_ehv_ivors
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b 2f
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1:
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ld r10,CPU_SPEC_FEATURES(r4)
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LOAD_REG_IMMEDIATE(r9,CPU_FTR_EMB_HV)
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andc r10,r10,r9
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std r10,CPU_SPEC_FEATURES(r4)
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2:
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mtlr r5
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blr
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#endif
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/* flush L1 data cache, it can apply to e500v2, e500mc and e5500 */
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_GLOBAL(flush_dcache_L1)
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mfmsr r10
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wrteei 0
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mfspr r3,SPRN_L1CFG0
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rlwinm r5,r3,9,3 /* Extract cache block size */
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twlgti r5,1 /* Only 32 and 64 byte cache blocks
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* are currently defined.
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*/
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li r4,32
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subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
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* log2(number of ways)
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*/
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slw r5,r4,r5 /* r5 = cache block size */
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rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
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mulli r7,r7,13 /* An 8-way cache will require 13
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* loads per set.
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*/
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slw r7,r7,r6
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/* save off HID0 and set DCFA */
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mfspr r8,SPRN_HID0
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ori r9,r8,HID0_DCFA@l
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mtspr SPRN_HID0,r9
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isync
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LOAD_REG_IMMEDIATE(r6, KERNELBASE)
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mr r4, r6
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mtctr r7
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1: lwz r3,0(r4) /* Load... */
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add r4,r4,r5
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bdnz 1b
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msync
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mr r4, r6
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mtctr r7
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1: dcbf 0,r4 /* ...and flush. */
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add r4,r4,r5
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bdnz 1b
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/* restore HID0 */
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mtspr SPRN_HID0,r8
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isync
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wrtee r10
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blr
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has_L2_cache:
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/* skip L2 cache on P2040/P2040E as they have no L2 cache */
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mfspr r3, SPRN_SVR
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/* shift right by 8 bits and clear E bit of SVR */
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rlwinm r4, r3, 24, ~0x800
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lis r3, SVR_P2040@h
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ori r3, r3, SVR_P2040@l
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cmpw r4, r3
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beq 1f
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li r3, 1
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blr
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1:
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li r3, 0
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blr
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/* flush backside L2 cache */
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flush_backside_L2_cache:
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mflr r10
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bl has_L2_cache
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mtlr r10
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cmpwi r3, 0
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beq 2f
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/* Flush the L2 cache */
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mfspr r3, SPRN_L2CSR0
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ori r3, r3, L2CSR0_L2FL@l
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msync
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isync
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mtspr SPRN_L2CSR0,r3
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isync
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/* check if it is complete */
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1: mfspr r3,SPRN_L2CSR0
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andi. r3, r3, L2CSR0_L2FL@l
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bne 1b
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2:
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blr
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_GLOBAL(cpu_down_flush_e500v2)
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mflr r0
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bl flush_dcache_L1
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mtlr r0
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blr
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_GLOBAL(cpu_down_flush_e500mc)
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_GLOBAL(cpu_down_flush_e5500)
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mflr r0
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bl flush_dcache_L1
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bl flush_backside_L2_cache
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mtlr r0
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blr
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/* L1 Data Cache of e6500 contains no modified data, no flush is required */
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_GLOBAL(cpu_down_flush_e6500)
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blr
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