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40272035e1
When the BPF routine doesn't call any function, the non volatile registers can be reallocated to volatile registers in order to avoid having to save them/restore on the stack. Before this patch, the test #359 ADD default X is: 0: 7c 64 1b 78 mr r4,r3 4: 38 60 00 00 li r3,0 8: 94 21 ff b0 stwu r1,-80(r1) c: 60 00 00 00 nop 10: 92 e1 00 2c stw r23,44(r1) 14: 93 01 00 30 stw r24,48(r1) 18: 93 21 00 34 stw r25,52(r1) 1c: 93 41 00 38 stw r26,56(r1) 20: 39 80 00 00 li r12,0 24: 39 60 00 00 li r11,0 28: 3b 40 00 00 li r26,0 2c: 3b 20 00 00 li r25,0 30: 7c 98 23 78 mr r24,r4 34: 7c 77 1b 78 mr r23,r3 38: 39 80 00 42 li r12,66 3c: 39 60 00 00 li r11,0 40: 7d 8c d2 14 add r12,r12,r26 44: 39 60 00 00 li r11,0 48: 7d 83 63 78 mr r3,r12 4c: 82 e1 00 2c lwz r23,44(r1) 50: 83 01 00 30 lwz r24,48(r1) 54: 83 21 00 34 lwz r25,52(r1) 58: 83 41 00 38 lwz r26,56(r1) 5c: 38 21 00 50 addi r1,r1,80 60: 4e 80 00 20 blr After this patch, the same test has become: 0: 7c 64 1b 78 mr r4,r3 4: 38 60 00 00 li r3,0 8: 94 21 ff b0 stwu r1,-80(r1) c: 60 00 00 00 nop 10: 39 80 00 00 li r12,0 14: 39 60 00 00 li r11,0 18: 39 00 00 00 li r8,0 1c: 38 e0 00 00 li r7,0 20: 7c 86 23 78 mr r6,r4 24: 7c 65 1b 78 mr r5,r3 28: 39 80 00 42 li r12,66 2c: 39 60 00 00 li r11,0 30: 7d 8c 42 14 add r12,r12,r8 34: 39 60 00 00 li r11,0 38: 7d 83 63 78 mr r3,r12 3c: 38 21 00 50 addi r1,r1,80 40: 4e 80 00 20 blr Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/b94562d7d2bb21aec89de0c40bb3cd91054b65a2.1616430991.git.christophe.leroy@csgroup.eu
91 lines
2.4 KiB
C
91 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* bpf_jit64.h: BPF JIT compiler for PPC64
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*
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* Copyright 2016 Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
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* IBM Corporation
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*/
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#ifndef _BPF_JIT64_H
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#define _BPF_JIT64_H
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#include "bpf_jit.h"
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/*
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* Stack layout:
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* Ensure the top half (upto local_tmp_var) stays consistent
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* with our redzone usage.
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*
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* [ prev sp ] <-------------
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* [ nv gpr save area ] 6*8 |
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* [ tail_call_cnt ] 8 |
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* [ local_tmp_var ] 8 |
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* fp (r31) --> [ ebpf stack space ] upto 512 |
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* [ frame header ] 32/112 |
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* sp (r1) ---> [ stack pointer ] --------------
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*/
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/* for gpr non volatile registers BPG_REG_6 to 10 */
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#define BPF_PPC_STACK_SAVE (6*8)
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/* for bpf JIT code internal usage */
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#define BPF_PPC_STACK_LOCALS 16
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/* stack frame excluding BPF stack, ensure this is quadword aligned */
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#define BPF_PPC_STACKFRAME (STACK_FRAME_MIN_SIZE + \
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BPF_PPC_STACK_LOCALS + BPF_PPC_STACK_SAVE)
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#ifndef __ASSEMBLY__
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/* BPF register usage */
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#define TMP_REG_1 (MAX_BPF_JIT_REG + 0)
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#define TMP_REG_2 (MAX_BPF_JIT_REG + 1)
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/* BPF to ppc register mappings */
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const int b2p[MAX_BPF_JIT_REG + 2] = {
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/* function return value */
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[BPF_REG_0] = 8,
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/* function arguments */
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[BPF_REG_1] = 3,
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[BPF_REG_2] = 4,
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[BPF_REG_3] = 5,
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[BPF_REG_4] = 6,
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[BPF_REG_5] = 7,
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/* non volatile registers */
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[BPF_REG_6] = 27,
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[BPF_REG_7] = 28,
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[BPF_REG_8] = 29,
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[BPF_REG_9] = 30,
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/* frame pointer aka BPF_REG_10 */
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[BPF_REG_FP] = 31,
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/* eBPF jit internal registers */
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[BPF_REG_AX] = 2,
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[TMP_REG_1] = 9,
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[TMP_REG_2] = 10
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};
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/* PPC NVR range -- update this if we ever use NVRs below r27 */
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#define BPF_PPC_NVR_MIN 27
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/*
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* WARNING: These can use TMP_REG_2 if the offset is not at word boundary,
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* so ensure that it isn't in use already.
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*/
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#define PPC_BPF_LL(r, base, i) do { \
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if ((i) % 4) { \
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EMIT(PPC_RAW_LI(b2p[TMP_REG_2], (i)));\
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EMIT(PPC_RAW_LDX(r, base, \
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b2p[TMP_REG_2])); \
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} else \
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EMIT(PPC_RAW_LD(r, base, i)); \
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} while(0)
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#define PPC_BPF_STL(r, base, i) do { \
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if ((i) % 4) { \
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EMIT(PPC_RAW_LI(b2p[TMP_REG_2], (i)));\
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EMIT(PPC_RAW_STDX(r, base, \
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b2p[TMP_REG_2])); \
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} else \
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EMIT(PPC_RAW_STD(r, base, i)); \
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} while(0)
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#define PPC_BPF_STLU(r, base, i) do { EMIT(PPC_RAW_STDU(r, base, i)); } while(0)
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#endif /* !__ASSEMBLY__ */
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#endif
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