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e28b003136
This adds a platform specific spu management abstraction and the coresponding routines to support the IBM Cell Blade. It also removes the hypervisor only resources that were included in struct spu. Three new platform specific routines are introduced, spu_enumerate_spus(), spu_create_spu() and spu_destroy_spu(). The underlying design uses a new type, struct spu_management_ops, to hold function pointers that the platform setup code is expected to initialize to instances appropriate to that platform. For the IBM Cell Blade support, I put the hypervisor only resources that were in struct spu into a platform specific data structure struct spu_pdata. Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
212 lines
5.2 KiB
C
212 lines
5.2 KiB
C
/*
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* Defines an spu hypervisor abstraction layer.
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*
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* Copyright 2006 Sony Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#if !defined(_SPU_PRIV1_H)
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#define _SPU_PRIV1_H
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#if defined(__KERNEL__)
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#include <linux/types.h>
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struct spu;
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/* access to priv1 registers */
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struct spu_priv1_ops {
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void (*int_mask_and) (struct spu *spu, int class, u64 mask);
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void (*int_mask_or) (struct spu *spu, int class, u64 mask);
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void (*int_mask_set) (struct spu *spu, int class, u64 mask);
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u64 (*int_mask_get) (struct spu *spu, int class);
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void (*int_stat_clear) (struct spu *spu, int class, u64 stat);
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u64 (*int_stat_get) (struct spu *spu, int class);
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void (*cpu_affinity_set) (struct spu *spu, int cpu);
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u64 (*mfc_dar_get) (struct spu *spu);
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u64 (*mfc_dsisr_get) (struct spu *spu);
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void (*mfc_dsisr_set) (struct spu *spu, u64 dsisr);
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void (*mfc_sdr_setup) (struct spu *spu);
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void (*mfc_sr1_set) (struct spu *spu, u64 sr1);
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u64 (*mfc_sr1_get) (struct spu *spu);
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void (*mfc_tclass_id_set) (struct spu *spu, u64 tclass_id);
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u64 (*mfc_tclass_id_get) (struct spu *spu);
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void (*tlb_invalidate) (struct spu *spu);
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void (*resource_allocation_groupID_set) (struct spu *spu, u64 id);
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u64 (*resource_allocation_groupID_get) (struct spu *spu);
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void (*resource_allocation_enable_set) (struct spu *spu, u64 enable);
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u64 (*resource_allocation_enable_get) (struct spu *spu);
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};
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extern const struct spu_priv1_ops* spu_priv1_ops;
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static inline void
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spu_int_mask_and (struct spu *spu, int class, u64 mask)
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{
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spu_priv1_ops->int_mask_and(spu, class, mask);
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}
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static inline void
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spu_int_mask_or (struct spu *spu, int class, u64 mask)
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{
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spu_priv1_ops->int_mask_or(spu, class, mask);
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}
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static inline void
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spu_int_mask_set (struct spu *spu, int class, u64 mask)
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{
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spu_priv1_ops->int_mask_set(spu, class, mask);
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}
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static inline u64
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spu_int_mask_get (struct spu *spu, int class)
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{
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return spu_priv1_ops->int_mask_get(spu, class);
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}
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static inline void
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spu_int_stat_clear (struct spu *spu, int class, u64 stat)
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{
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spu_priv1_ops->int_stat_clear(spu, class, stat);
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}
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static inline u64
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spu_int_stat_get (struct spu *spu, int class)
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{
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return spu_priv1_ops->int_stat_get (spu, class);
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}
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static inline void
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spu_cpu_affinity_set (struct spu *spu, int cpu)
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{
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spu_priv1_ops->cpu_affinity_set(spu, cpu);
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}
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static inline u64
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spu_mfc_dar_get (struct spu *spu)
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{
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return spu_priv1_ops->mfc_dar_get(spu);
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}
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static inline u64
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spu_mfc_dsisr_get (struct spu *spu)
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{
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return spu_priv1_ops->mfc_dsisr_get(spu);
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}
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static inline void
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spu_mfc_dsisr_set (struct spu *spu, u64 dsisr)
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{
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spu_priv1_ops->mfc_dsisr_set(spu, dsisr);
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}
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static inline void
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spu_mfc_sdr_setup (struct spu *spu)
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{
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spu_priv1_ops->mfc_sdr_setup(spu);
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}
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static inline void
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spu_mfc_sr1_set (struct spu *spu, u64 sr1)
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{
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spu_priv1_ops->mfc_sr1_set(spu, sr1);
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}
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static inline u64
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spu_mfc_sr1_get (struct spu *spu)
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{
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return spu_priv1_ops->mfc_sr1_get(spu);
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}
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static inline void
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spu_mfc_tclass_id_set (struct spu *spu, u64 tclass_id)
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{
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spu_priv1_ops->mfc_tclass_id_set(spu, tclass_id);
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}
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static inline u64
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spu_mfc_tclass_id_get (struct spu *spu)
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{
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return spu_priv1_ops->mfc_tclass_id_get(spu);
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}
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static inline void
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spu_tlb_invalidate (struct spu *spu)
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{
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spu_priv1_ops->tlb_invalidate(spu);
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}
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static inline void
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spu_resource_allocation_groupID_set (struct spu *spu, u64 id)
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{
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spu_priv1_ops->resource_allocation_groupID_set(spu, id);
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}
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static inline u64
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spu_resource_allocation_groupID_get (struct spu *spu)
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{
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return spu_priv1_ops->resource_allocation_groupID_get(spu);
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}
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static inline void
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spu_resource_allocation_enable_set (struct spu *spu, u64 enable)
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{
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spu_priv1_ops->resource_allocation_enable_set(spu, enable);
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}
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static inline u64
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spu_resource_allocation_enable_get (struct spu *spu)
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{
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return spu_priv1_ops->resource_allocation_enable_get(spu);
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}
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/* spu management abstraction */
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struct spu_management_ops {
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int (*enumerate_spus)(int (*fn)(void *data));
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int (*create_spu)(struct spu *spu, void *data);
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int (*destroy_spu)(struct spu *spu);
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};
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extern const struct spu_management_ops* spu_management_ops;
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static inline int
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spu_enumerate_spus (int (*fn)(void *data))
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{
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return spu_management_ops->enumerate_spus(fn);
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}
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static inline int
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spu_create_spu (struct spu *spu, void *data)
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{
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return spu_management_ops->create_spu(spu, data);
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}
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static inline int
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spu_destroy_spu (struct spu *spu)
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{
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return spu_management_ops->destroy_spu(spu);
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}
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/*
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* The declarations folowing are put here for convenience
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* and only intended to be used by the platform setup code.
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*/
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extern const struct spu_priv1_ops spu_priv1_mmio_ops;
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extern const struct spu_management_ops spu_management_of_ops;
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#endif /* __KERNEL__ */
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#endif
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