204 lines
6.4 KiB
YAML
204 lines
6.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Brcmstb PCIe Host Controller
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maintainers:
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- Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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properties:
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compatible:
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items:
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- enum:
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- brcm,bcm2711-pcie # The Raspberry Pi 4
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- brcm,bcm4908-pcie
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- brcm,bcm7211-pcie # Broadcom STB version of RPi4
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- brcm,bcm7278-pcie # Broadcom 7278 Arm
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- brcm,bcm7216-pcie # Broadcom 7216 Arm
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- brcm,bcm7445-pcie # Broadcom 7445 Arm
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- brcm,bcm7425-pcie # Broadcom 7425 MIPs
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- brcm,bcm7435-pcie # Broadcom 7435 MIPs
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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items:
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- description: PCIe host controller
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- description: builtin MSI controller
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interrupt-names:
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minItems: 1
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items:
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- const: pcie
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- const: msi
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ranges:
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minItems: 1
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maxItems: 4
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dma-ranges:
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minItems: 1
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maxItems: 6
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: sw_pcie
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msi-controller:
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description: Identifies the node as an MSI controller.
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msi-parent:
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description: MSI controller the device is capable of using.
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brcm,enable-ssc:
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description: Indicates usage of spread-spectrum clocking.
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type: boolean
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aspm-no-l0s: true
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brcm,clkreq-mode:
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description: A string that determines the operating
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clkreq mode of the PCIe RC HW with respect to controlling the refclk
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signal. There are three different modes -- "safe", which drives the
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refclk signal unconditionally and will work for all devices but does
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not provide any power savings; "no-l1ss" -- which provides Clock
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Power Management, L0s, and L1, but cannot provide L1 substate (L1SS)
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power savings. If the downstream device connected to the RC is L1SS
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capable AND the OS enables L1SS, all PCIe traffic may abruptly halt,
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potentially hanging the system; "default" -- which provides L0s, L1,
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and L1SS, but not compliant to provide Clock Power Management;
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specifically, may not be able to meet the T_CLRon max timing of 400ns
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as specified in "Dynamic Clock Control", section 3.2.5.2.2 PCI
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Express Mini CEM 2.1 specification. This situation is atypical and
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should happen only with older devices.
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$ref: /schemas/types.yaml#/definitions/string
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enum: [ safe, no-l1ss, default ]
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brcm,scb-sizes:
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description: u64 giving the 64bit PCIe memory
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viewport size of a memory controller. There may be up to
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three controllers, and each size must be a power of two
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with a size greater or equal to the amount of memory the
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controller supports. Note that each memory controller
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may have two component regions -- base and extended -- so
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this information cannot be deduced from the dma-ranges.
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$ref: /schemas/types.yaml#/definitions/uint64-array
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items:
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minItems: 1
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maxItems: 3
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required:
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- compatible
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- reg
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- ranges
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- dma-ranges
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- "#interrupt-cells"
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- interrupts
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- interrupt-names
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- interrupt-map-mask
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- interrupt-map
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- msi-controller
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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- $ref: /schemas/interrupt-controller/msi-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: brcm,bcm4908-pcie
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then:
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properties:
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resets:
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items:
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- description: reset controller handling the PERST# signal
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reset-names:
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items:
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- const: perst
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required:
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- resets
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- reset-names
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- if:
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properties:
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compatible:
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contains:
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const: brcm,bcm7216-pcie
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then:
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properties:
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resets:
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items:
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- description: phandle pointing to the RESCAL reset controller
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reset-names:
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items:
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- const: rescal
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required:
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- resets
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- reset-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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scb {
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#address-cells = <2>;
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#size-cells = <1>;
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pcie0: pcie@7d500000 {
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compatible = "brcm,bcm2711-pcie";
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reg = <0x0 0x7d500000 0x9310>;
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "msi";
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie0>;
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msi-controller;
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ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
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dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
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<0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
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brcm,enable-ssc;
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brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
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/* PCIe bridge, Root Port */
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pci@0,0 {
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x0 0x0 0x0 0x0 0x0>;
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compatible = "pciclass,0604";
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device_type = "pci";
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vpcie3v3-supply = <&vreg7>;
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ranges;
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/* PCIe endpoint */
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pci-ep@0,0 {
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assigned-addresses =
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<0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
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reg = <0x0 0x0 0x0 0x0 0x0>;
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compatible = "pci14e4,1688";
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};
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};
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};
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};
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