mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 19:29:37 +00:00
![Bjorn Helgaas](/assets/img/avatar_default.png)
* pci/host-designware: PCI: dwc: Clear MSI interrupt status after it is handled, not before PCI: qcom: Allow ->post_init() to fail PCI: qcom: Don't unroll init if ->init() fails PCI: dwc: designware: Handle ->host_init() failures PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specifically PCI: dwc: designware: Make dw_pcie_prog_*_atu_unroll() static
272 lines
7.3 KiB
C
272 lines
7.3 KiB
C
/*
|
|
* PCIe host controller driver for Marvell Armada-8K SoCs
|
|
*
|
|
* Armada-8K PCIe Glue Layer Source Code
|
|
*
|
|
* Copyright (C) 2016 Marvell Technology Group Ltd.
|
|
*
|
|
* Author: Yehuda Yitshak <yehuday@marvell.com>
|
|
* Author: Shadi Ammouri <shadi@marvell.com>
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public
|
|
* License version 2. This program is licensed "as is" without any
|
|
* warranty of any kind, whether express or implied.
|
|
*/
|
|
|
|
#include <linux/clk.h>
|
|
#include <linux/delay.h>
|
|
#include <linux/interrupt.h>
|
|
#include <linux/kernel.h>
|
|
#include <linux/init.h>
|
|
#include <linux/of.h>
|
|
#include <linux/pci.h>
|
|
#include <linux/phy/phy.h>
|
|
#include <linux/platform_device.h>
|
|
#include <linux/resource.h>
|
|
#include <linux/of_pci.h>
|
|
#include <linux/of_irq.h>
|
|
|
|
#include "pcie-designware.h"
|
|
|
|
struct armada8k_pcie {
|
|
struct dw_pcie *pci;
|
|
struct clk *clk;
|
|
};
|
|
|
|
#define PCIE_VENDOR_REGS_OFFSET 0x8000
|
|
|
|
#define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0)
|
|
#define PCIE_APP_LTSSM_EN BIT(2)
|
|
#define PCIE_DEVICE_TYPE_SHIFT 4
|
|
#define PCIE_DEVICE_TYPE_MASK 0xF
|
|
#define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */
|
|
|
|
#define PCIE_GLOBAL_STATUS_REG (PCIE_VENDOR_REGS_OFFSET + 0x8)
|
|
#define PCIE_GLB_STS_RDLH_LINK_UP BIT(1)
|
|
#define PCIE_GLB_STS_PHY_LINK_UP BIT(9)
|
|
|
|
#define PCIE_GLOBAL_INT_CAUSE1_REG (PCIE_VENDOR_REGS_OFFSET + 0x1C)
|
|
#define PCIE_GLOBAL_INT_MASK1_REG (PCIE_VENDOR_REGS_OFFSET + 0x20)
|
|
#define PCIE_INT_A_ASSERT_MASK BIT(9)
|
|
#define PCIE_INT_B_ASSERT_MASK BIT(10)
|
|
#define PCIE_INT_C_ASSERT_MASK BIT(11)
|
|
#define PCIE_INT_D_ASSERT_MASK BIT(12)
|
|
|
|
#define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50)
|
|
#define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54)
|
|
#define PCIE_ARUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x5C)
|
|
#define PCIE_AWUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x60)
|
|
/*
|
|
* AR/AW Cache defauls: Normal memory, Write-Back, Read / Write
|
|
* allocate
|
|
*/
|
|
#define ARCACHE_DEFAULT_VALUE 0x3511
|
|
#define AWCACHE_DEFAULT_VALUE 0x5311
|
|
|
|
#define DOMAIN_OUTER_SHAREABLE 0x2
|
|
#define AX_USER_DOMAIN_MASK 0x3
|
|
#define AX_USER_DOMAIN_SHIFT 4
|
|
|
|
#define to_armada8k_pcie(x) dev_get_drvdata((x)->dev)
|
|
|
|
static int armada8k_pcie_link_up(struct dw_pcie *pci)
|
|
{
|
|
u32 reg;
|
|
u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
|
|
|
|
reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG);
|
|
|
|
if ((reg & mask) == mask)
|
|
return 1;
|
|
|
|
dev_dbg(pci->dev, "No link detected (Global-Status: 0x%08x).\n", reg);
|
|
return 0;
|
|
}
|
|
|
|
static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie)
|
|
{
|
|
struct dw_pcie *pci = pcie->pci;
|
|
u32 reg;
|
|
|
|
if (!dw_pcie_link_up(pci)) {
|
|
/* Disable LTSSM state machine to enable configuration */
|
|
reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
|
|
reg &= ~(PCIE_APP_LTSSM_EN);
|
|
dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
|
|
}
|
|
|
|
/* Set the device to root complex mode */
|
|
reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
|
|
reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT);
|
|
reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT;
|
|
dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
|
|
|
|
/* Set the PCIe master AxCache attributes */
|
|
dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE);
|
|
dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE);
|
|
|
|
/* Set the PCIe master AxDomain attributes */
|
|
reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG);
|
|
reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
|
|
reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
|
|
dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg);
|
|
|
|
reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG);
|
|
reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
|
|
reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
|
|
dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg);
|
|
|
|
/* Enable INT A-D interrupts */
|
|
reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG);
|
|
reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK |
|
|
PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
|
|
dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg);
|
|
|
|
if (!dw_pcie_link_up(pci)) {
|
|
/* Configuration done. Start LTSSM */
|
|
reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
|
|
reg |= PCIE_APP_LTSSM_EN;
|
|
dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
|
|
}
|
|
|
|
/* Wait until the link becomes active again */
|
|
if (dw_pcie_wait_for_link(pci))
|
|
dev_err(pci->dev, "Link not up after reconfiguration\n");
|
|
}
|
|
|
|
static int armada8k_pcie_host_init(struct pcie_port *pp)
|
|
{
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
|
struct armada8k_pcie *pcie = to_armada8k_pcie(pci);
|
|
|
|
dw_pcie_setup_rc(pp);
|
|
armada8k_pcie_establish_link(pcie);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
|
|
{
|
|
struct armada8k_pcie *pcie = arg;
|
|
struct dw_pcie *pci = pcie->pci;
|
|
u32 val;
|
|
|
|
/*
|
|
* Interrupts are directly handled by the device driver of the
|
|
* PCI device. However, they are also latched into the PCIe
|
|
* controller, so we simply discard them.
|
|
*/
|
|
val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG);
|
|
dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static const struct dw_pcie_host_ops armada8k_pcie_host_ops = {
|
|
.host_init = armada8k_pcie_host_init,
|
|
};
|
|
|
|
static int armada8k_add_pcie_port(struct armada8k_pcie *pcie,
|
|
struct platform_device *pdev)
|
|
{
|
|
struct dw_pcie *pci = pcie->pci;
|
|
struct pcie_port *pp = &pci->pp;
|
|
struct device *dev = &pdev->dev;
|
|
int ret;
|
|
|
|
pp->root_bus_nr = -1;
|
|
pp->ops = &armada8k_pcie_host_ops;
|
|
|
|
pp->irq = platform_get_irq(pdev, 0);
|
|
if (pp->irq < 0) {
|
|
dev_err(dev, "failed to get irq for port\n");
|
|
return pp->irq;
|
|
}
|
|
|
|
ret = devm_request_irq(dev, pp->irq, armada8k_pcie_irq_handler,
|
|
IRQF_SHARED, "armada8k-pcie", pcie);
|
|
if (ret) {
|
|
dev_err(dev, "failed to request irq %d\n", pp->irq);
|
|
return ret;
|
|
}
|
|
|
|
ret = dw_pcie_host_init(pp);
|
|
if (ret) {
|
|
dev_err(dev, "failed to initialize host: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dw_pcie_ops dw_pcie_ops = {
|
|
.link_up = armada8k_pcie_link_up,
|
|
};
|
|
|
|
static int armada8k_pcie_probe(struct platform_device *pdev)
|
|
{
|
|
struct dw_pcie *pci;
|
|
struct armada8k_pcie *pcie;
|
|
struct device *dev = &pdev->dev;
|
|
struct resource *base;
|
|
int ret;
|
|
|
|
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
|
|
if (!pcie)
|
|
return -ENOMEM;
|
|
|
|
pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
|
|
if (!pci)
|
|
return -ENOMEM;
|
|
|
|
pci->dev = dev;
|
|
pci->ops = &dw_pcie_ops;
|
|
|
|
pcie->pci = pci;
|
|
|
|
pcie->clk = devm_clk_get(dev, NULL);
|
|
if (IS_ERR(pcie->clk))
|
|
return PTR_ERR(pcie->clk);
|
|
|
|
ret = clk_prepare_enable(pcie->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Get the dw-pcie unit configuration/control registers base. */
|
|
base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
|
|
pci->dbi_base = devm_pci_remap_cfg_resource(dev, base);
|
|
if (IS_ERR(pci->dbi_base)) {
|
|
dev_err(dev, "couldn't remap regs base %p\n", base);
|
|
ret = PTR_ERR(pci->dbi_base);
|
|
goto fail;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, pcie);
|
|
|
|
ret = armada8k_add_pcie_port(pcie, pdev);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
if (!IS_ERR(pcie->clk))
|
|
clk_disable_unprepare(pcie->clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id armada8k_pcie_of_match[] = {
|
|
{ .compatible = "marvell,armada8k-pcie", },
|
|
{},
|
|
};
|
|
|
|
static struct platform_driver armada8k_pcie_driver = {
|
|
.probe = armada8k_pcie_probe,
|
|
.driver = {
|
|
.name = "armada8k-pcie",
|
|
.of_match_table = of_match_ptr(armada8k_pcie_of_match),
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
};
|
|
builtin_platform_driver(armada8k_pcie_driver);
|