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![Bjorn Helgaas](/assets/img/avatar_default.png)
* pci/trivial: PCI: Fix typos and whitespace errors PCI: Remove unused "res" variable from pci_resource_io() PCI: Correct kernel-doc of pci_vpd_srdt_size(), pci_vpd_srdt_tag()
652 lines
16 KiB
C
652 lines
16 KiB
C
/*
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* Synopsys DesignWare PCIe host controller driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/pci_regs.h>
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#include <linux/platform_device.h>
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#include "pcie-designware.h"
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static struct pci_ops dw_pcie_ops;
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static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
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u32 *val)
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{
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struct dw_pcie *pci;
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if (pp->ops->rd_own_conf)
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return pp->ops->rd_own_conf(pp, where, size, val);
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pci = to_dw_pcie_from_pp(pp);
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return dw_pcie_read(pci->dbi_base + where, size, val);
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}
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static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
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u32 val)
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{
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struct dw_pcie *pci;
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if (pp->ops->wr_own_conf)
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return pp->ops->wr_own_conf(pp, where, size, val);
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pci = to_dw_pcie_from_pp(pp);
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return dw_pcie_write(pci->dbi_base + where, size, val);
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}
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static struct irq_chip dw_msi_irq_chip = {
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.name = "PCI-MSI",
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.irq_enable = pci_msi_unmask_irq,
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.irq_disable = pci_msi_mask_irq,
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.irq_mask = pci_msi_mask_irq,
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.irq_unmask = pci_msi_unmask_irq,
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};
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/* MSI int handler */
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irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
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{
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u32 val;
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int i, pos, irq;
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irqreturn_t ret = IRQ_NONE;
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for (i = 0; i < MAX_MSI_CTRLS; i++) {
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dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
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&val);
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if (!val)
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continue;
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ret = IRQ_HANDLED;
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pos = 0;
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while ((pos = find_next_bit((unsigned long *) &val, 32,
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pos)) != 32) {
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irq = irq_find_mapping(pp->irq_domain, i * 32 + pos);
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generic_handle_irq(irq);
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12,
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4, 1 << pos);
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pos++;
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}
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}
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return ret;
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}
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void dw_pcie_msi_init(struct pcie_port *pp)
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{
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u64 msi_target;
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pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
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msi_target = virt_to_phys((void *)pp->msi_data);
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/* program the msi_data */
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dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
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(u32)(msi_target & 0xffffffff));
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dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
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(u32)(msi_target >> 32 & 0xffffffff));
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}
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static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
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{
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unsigned int res, bit, val;
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res = (irq / 32) * 12;
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bit = irq % 32;
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dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
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val &= ~(1 << bit);
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
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}
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static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
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unsigned int nvec, unsigned int pos)
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{
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unsigned int i;
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for (i = 0; i < nvec; i++) {
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irq_set_msi_desc_off(irq_base, i, NULL);
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/* Disable corresponding interrupt on MSI controller */
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if (pp->ops->msi_clear_irq)
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pp->ops->msi_clear_irq(pp, pos + i);
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else
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dw_pcie_msi_clear_irq(pp, pos + i);
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}
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bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
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}
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static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
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{
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unsigned int res, bit, val;
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res = (irq / 32) * 12;
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bit = irq % 32;
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dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
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val |= 1 << bit;
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
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}
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static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
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{
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int irq, pos0, i;
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struct pcie_port *pp;
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pp = (struct pcie_port *)msi_desc_to_pci_sysdata(desc);
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pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
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order_base_2(no_irqs));
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if (pos0 < 0)
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goto no_valid_irq;
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irq = irq_find_mapping(pp->irq_domain, pos0);
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if (!irq)
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goto no_valid_irq;
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/*
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* irq_create_mapping (called from dw_pcie_host_init) pre-allocates
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* descs so there is no need to allocate descs here. We can therefore
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* assume that if irq_find_mapping above returns non-zero, then the
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* descs are also successfully allocated.
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*/
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for (i = 0; i < no_irqs; i++) {
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if (irq_set_msi_desc_off(irq, i, desc) != 0) {
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clear_irq_range(pp, irq, i, pos0);
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goto no_valid_irq;
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}
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/*Enable corresponding interrupt in MSI interrupt controller */
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if (pp->ops->msi_set_irq)
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pp->ops->msi_set_irq(pp, pos0 + i);
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else
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dw_pcie_msi_set_irq(pp, pos0 + i);
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}
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*pos = pos0;
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desc->nvec_used = no_irqs;
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desc->msi_attrib.multiple = order_base_2(no_irqs);
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return irq;
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no_valid_irq:
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*pos = pos0;
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return -ENOSPC;
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}
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static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
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{
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struct msi_msg msg;
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u64 msi_target;
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if (pp->ops->get_msi_addr)
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msi_target = pp->ops->get_msi_addr(pp);
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else
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msi_target = virt_to_phys((void *)pp->msi_data);
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msg.address_lo = (u32)(msi_target & 0xffffffff);
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msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
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if (pp->ops->get_msi_data)
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msg.data = pp->ops->get_msi_data(pp, pos);
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else
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msg.data = pos;
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pci_write_msi_msg(irq, &msg);
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}
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static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
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struct msi_desc *desc)
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{
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int irq, pos;
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struct pcie_port *pp = pdev->bus->sysdata;
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if (desc->msi_attrib.is_msix)
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return -EINVAL;
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irq = assign_irq(1, desc, &pos);
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if (irq < 0)
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return irq;
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dw_msi_setup_msg(pp, irq, pos);
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return 0;
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}
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static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev,
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int nvec, int type)
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{
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#ifdef CONFIG_PCI_MSI
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int irq, pos;
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struct msi_desc *desc;
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struct pcie_port *pp = pdev->bus->sysdata;
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/* MSI-X interrupts are not supported */
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if (type == PCI_CAP_ID_MSIX)
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return -EINVAL;
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WARN_ON(!list_is_singular(&pdev->dev.msi_list));
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desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
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irq = assign_irq(nvec, desc, &pos);
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if (irq < 0)
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return irq;
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dw_msi_setup_msg(pp, irq, pos);
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return 0;
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#else
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return -EINVAL;
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#endif
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}
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static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
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{
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struct irq_data *data = irq_get_irq_data(irq);
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struct msi_desc *msi = irq_data_get_msi_desc(data);
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struct pcie_port *pp = (struct pcie_port *)msi_desc_to_pci_sysdata(msi);
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clear_irq_range(pp, irq, 1, data->hwirq);
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}
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static struct msi_controller dw_pcie_msi_chip = {
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.setup_irq = dw_msi_setup_irq,
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.setup_irqs = dw_msi_setup_irqs,
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.teardown_irq = dw_msi_teardown_irq,
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};
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static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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}
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static const struct irq_domain_ops msi_domain_ops = {
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.map = dw_pcie_msi_map,
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};
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int dw_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct device *dev = pci->dev;
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struct device_node *np = dev->of_node;
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struct platform_device *pdev = to_platform_device(dev);
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struct pci_bus *bus, *child;
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struct pci_host_bridge *bridge;
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struct resource *cfg_res;
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int i, ret;
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struct resource_entry *win, *tmp;
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cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
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if (cfg_res) {
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pp->cfg0_size = resource_size(cfg_res) / 2;
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pp->cfg1_size = resource_size(cfg_res) / 2;
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pp->cfg0_base = cfg_res->start;
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pp->cfg1_base = cfg_res->start + pp->cfg0_size;
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} else if (!pp->va_cfg0_base) {
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dev_err(dev, "missing *config* reg space\n");
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}
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bridge = pci_alloc_host_bridge(0);
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if (!bridge)
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return -ENOMEM;
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ret = of_pci_get_host_bridge_resources(np, 0, 0xff,
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&bridge->windows, &pp->io_base);
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if (ret)
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return ret;
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ret = devm_request_pci_bus_resources(dev, &bridge->windows);
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if (ret)
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goto error;
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/* Get the I/O and memory ranges from DT */
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resource_list_for_each_entry_safe(win, tmp, &bridge->windows) {
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switch (resource_type(win->res)) {
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case IORESOURCE_IO:
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ret = pci_remap_iospace(win->res, pp->io_base);
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if (ret) {
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dev_warn(dev, "error %d: failed to map resource %pR\n",
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ret, win->res);
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resource_list_destroy_entry(win);
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} else {
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pp->io = win->res;
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pp->io->name = "I/O";
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pp->io_size = resource_size(pp->io);
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pp->io_bus_addr = pp->io->start - win->offset;
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}
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break;
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case IORESOURCE_MEM:
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pp->mem = win->res;
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pp->mem->name = "MEM";
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pp->mem_size = resource_size(pp->mem);
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pp->mem_bus_addr = pp->mem->start - win->offset;
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break;
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case 0:
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pp->cfg = win->res;
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pp->cfg0_size = resource_size(pp->cfg) / 2;
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pp->cfg1_size = resource_size(pp->cfg) / 2;
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pp->cfg0_base = pp->cfg->start;
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pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
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break;
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case IORESOURCE_BUS:
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pp->busn = win->res;
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break;
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}
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}
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if (!pci->dbi_base) {
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pci->dbi_base = devm_pci_remap_cfgspace(dev,
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pp->cfg->start,
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resource_size(pp->cfg));
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if (!pci->dbi_base) {
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dev_err(dev, "error with ioremap\n");
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ret = -ENOMEM;
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goto error;
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}
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}
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pp->mem_base = pp->mem->start;
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if (!pp->va_cfg0_base) {
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pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,
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pp->cfg0_base, pp->cfg0_size);
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if (!pp->va_cfg0_base) {
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dev_err(dev, "error with ioremap in function\n");
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ret = -ENOMEM;
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goto error;
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}
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}
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if (!pp->va_cfg1_base) {
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pp->va_cfg1_base = devm_pci_remap_cfgspace(dev,
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pp->cfg1_base,
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pp->cfg1_size);
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if (!pp->va_cfg1_base) {
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dev_err(dev, "error with ioremap\n");
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ret = -ENOMEM;
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goto error;
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}
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}
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ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
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if (ret)
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pci->num_viewport = 2;
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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if (!pp->ops->msi_host_init) {
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pp->irq_domain = irq_domain_add_linear(dev->of_node,
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MAX_MSI_IRQS, &msi_domain_ops,
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&dw_pcie_msi_chip);
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if (!pp->irq_domain) {
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dev_err(dev, "irq domain init failed\n");
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ret = -ENXIO;
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goto error;
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}
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for (i = 0; i < MAX_MSI_IRQS; i++)
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irq_create_mapping(pp->irq_domain, i);
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} else {
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ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
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if (ret < 0)
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goto error;
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}
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}
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if (pp->ops->host_init) {
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ret = pp->ops->host_init(pp);
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if (ret)
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goto error;
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}
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pp->root_bus_nr = pp->busn->start;
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bridge->dev.parent = dev;
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bridge->sysdata = pp;
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bridge->busnr = pp->root_bus_nr;
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bridge->ops = &dw_pcie_ops;
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bridge->map_irq = of_irq_parse_and_map_pci;
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bridge->swizzle_irq = pci_common_swizzle;
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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bridge->msi = &dw_pcie_msi_chip;
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dw_pcie_msi_chip.dev = dev;
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}
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ret = pci_scan_root_bus_bridge(bridge);
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if (ret)
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goto error;
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bus = bridge->bus;
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if (pp->ops->scan_bus)
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pp->ops->scan_bus(pp);
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pci_bus_size_bridges(bus);
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pci_bus_assign_resources(bus);
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list_for_each_entry(child, &bus->children, node)
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pcie_bus_configure_settings(child);
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pci_bus_add_devices(bus);
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return 0;
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error:
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pci_free_host_bridge(bridge);
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return ret;
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}
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static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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u32 devfn, int where, int size, u32 *val)
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{
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int ret, type;
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u32 busdev, cfg_size;
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u64 cpu_addr;
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void __iomem *va_cfg_base;
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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if (pp->ops->rd_other_conf)
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return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
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busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
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PCIE_ATU_FUNC(PCI_FUNC(devfn));
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if (bus->parent->number == pp->root_bus_nr) {
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type = PCIE_ATU_TYPE_CFG0;
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cpu_addr = pp->cfg0_base;
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cfg_size = pp->cfg0_size;
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va_cfg_base = pp->va_cfg0_base;
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} else {
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type = PCIE_ATU_TYPE_CFG1;
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cpu_addr = pp->cfg1_base;
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cfg_size = pp->cfg1_size;
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va_cfg_base = pp->va_cfg1_base;
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}
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dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
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type, cpu_addr,
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busdev, cfg_size);
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ret = dw_pcie_read(va_cfg_base + where, size, val);
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if (pci->num_viewport <= 2)
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dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_IO, pp->io_base,
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pp->io_bus_addr, pp->io_size);
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|
|
return ret;
|
|
}
|
|
|
|
static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
|
|
u32 devfn, int where, int size, u32 val)
|
|
{
|
|
int ret, type;
|
|
u32 busdev, cfg_size;
|
|
u64 cpu_addr;
|
|
void __iomem *va_cfg_base;
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
|
|
|
if (pp->ops->wr_other_conf)
|
|
return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
|
|
|
|
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
|
|
PCIE_ATU_FUNC(PCI_FUNC(devfn));
|
|
|
|
if (bus->parent->number == pp->root_bus_nr) {
|
|
type = PCIE_ATU_TYPE_CFG0;
|
|
cpu_addr = pp->cfg0_base;
|
|
cfg_size = pp->cfg0_size;
|
|
va_cfg_base = pp->va_cfg0_base;
|
|
} else {
|
|
type = PCIE_ATU_TYPE_CFG1;
|
|
cpu_addr = pp->cfg1_base;
|
|
cfg_size = pp->cfg1_size;
|
|
va_cfg_base = pp->va_cfg1_base;
|
|
}
|
|
|
|
dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
|
|
type, cpu_addr,
|
|
busdev, cfg_size);
|
|
ret = dw_pcie_write(va_cfg_base + where, size, val);
|
|
if (pci->num_viewport <= 2)
|
|
dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
|
|
PCIE_ATU_TYPE_IO, pp->io_base,
|
|
pp->io_bus_addr, pp->io_size);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,
|
|
int dev)
|
|
{
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
|
|
|
/* If there is no link, then there is no device */
|
|
if (bus->number != pp->root_bus_nr) {
|
|
if (!dw_pcie_link_up(pci))
|
|
return 0;
|
|
}
|
|
|
|
/* access only one slot on each root port */
|
|
if (bus->number == pp->root_bus_nr && dev > 0)
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
|
|
int size, u32 *val)
|
|
{
|
|
struct pcie_port *pp = bus->sysdata;
|
|
|
|
if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) {
|
|
*val = 0xffffffff;
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
}
|
|
|
|
if (bus->number == pp->root_bus_nr)
|
|
return dw_pcie_rd_own_conf(pp, where, size, val);
|
|
|
|
return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
|
|
}
|
|
|
|
static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
|
|
int where, int size, u32 val)
|
|
{
|
|
struct pcie_port *pp = bus->sysdata;
|
|
|
|
if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn)))
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
if (bus->number == pp->root_bus_nr)
|
|
return dw_pcie_wr_own_conf(pp, where, size, val);
|
|
|
|
return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
|
|
}
|
|
|
|
static struct pci_ops dw_pcie_ops = {
|
|
.read = dw_pcie_rd_conf,
|
|
.write = dw_pcie_wr_conf,
|
|
};
|
|
|
|
static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
|
|
{
|
|
u32 val;
|
|
|
|
val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
|
|
if (val == 0xffffffff)
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void dw_pcie_setup_rc(struct pcie_port *pp)
|
|
{
|
|
u32 val;
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
|
|
|
dw_pcie_setup(pci);
|
|
|
|
/* setup RC BARs */
|
|
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
|
|
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
|
|
|
|
/* setup interrupt pins */
|
|
dw_pcie_dbi_ro_wr_en(pci);
|
|
val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
|
|
val &= 0xffff00ff;
|
|
val |= 0x00000100;
|
|
dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
|
|
dw_pcie_dbi_ro_wr_dis(pci);
|
|
|
|
/* setup bus numbers */
|
|
val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
|
|
val &= 0xff000000;
|
|
val |= 0x00010100;
|
|
dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
|
|
|
|
/* setup command register */
|
|
val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
|
|
val &= 0xffff0000;
|
|
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
|
|
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
|
|
dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
|
|
|
|
/*
|
|
* If the platform provides ->rd_other_conf, it means the platform
|
|
* uses its own address translation component rather than ATU, so
|
|
* we should not program the ATU here.
|
|
*/
|
|
if (!pp->ops->rd_other_conf) {
|
|
/* get iATU unroll support */
|
|
pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
|
|
dev_dbg(pci->dev, "iATU unroll: %s\n",
|
|
pci->iatu_unroll_enabled ? "enabled" : "disabled");
|
|
|
|
dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
|
|
PCIE_ATU_TYPE_MEM, pp->mem_base,
|
|
pp->mem_bus_addr, pp->mem_size);
|
|
if (pci->num_viewport > 2)
|
|
dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2,
|
|
PCIE_ATU_TYPE_IO, pp->io_base,
|
|
pp->io_bus_addr, pp->io_size);
|
|
}
|
|
|
|
dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
|
|
|
|
/* Enable write permission for the DBI read-only register */
|
|
dw_pcie_dbi_ro_wr_en(pci);
|
|
/* program correct class for RC */
|
|
dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
|
|
/* Better disable write permission right after the update */
|
|
dw_pcie_dbi_ro_wr_dis(pci);
|
|
|
|
dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
|
|
val |= PORT_LOGIC_SPEED_CHANGE;
|
|
dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
|
|
}
|