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![Bhumika Goyal](/assets/img/avatar_default.png)
Make this structure const as it is only stored in the ops field of a pcie_port structure, which is of type const. Done using Coccinelle. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
401 lines
9.4 KiB
C
401 lines
9.4 KiB
C
/*
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* PCIe host controller driver for HiSilicon SoCs
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*
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* Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
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*
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* Authors: Zhou Wang <wangzhou1@hisilicon.com>
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* Dacai Zhu <zhudacai@hisilicon.com>
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* Gabriele Paoloni <gabriele.paoloni@huawei.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/platform_device.h>
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#include <linux/of_device.h>
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#include <linux/pci.h>
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#include <linux/pci-acpi.h>
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#include <linux/pci-ecam.h>
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#include <linux/regmap.h>
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#include "../pci.h"
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#if defined(CONFIG_PCI_HISI) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
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static int hisi_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
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int size, u32 *val)
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{
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struct pci_config_window *cfg = bus->sysdata;
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int dev = PCI_SLOT(devfn);
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if (bus->number == cfg->busr.start) {
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/* access only one slot on each root port */
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if (dev > 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return pci_generic_config_read32(bus, devfn, where,
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size, val);
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}
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return pci_generic_config_read(bus, devfn, where, size, val);
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}
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static int hisi_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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int where, int size, u32 val)
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{
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struct pci_config_window *cfg = bus->sysdata;
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int dev = PCI_SLOT(devfn);
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if (bus->number == cfg->busr.start) {
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/* access only one slot on each root port */
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if (dev > 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return pci_generic_config_write32(bus, devfn, where,
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size, val);
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}
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return pci_generic_config_write(bus, devfn, where, size, val);
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}
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static void __iomem *hisi_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
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int where)
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{
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struct pci_config_window *cfg = bus->sysdata;
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void __iomem *reg_base = cfg->priv;
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if (bus->number == cfg->busr.start)
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return reg_base + where;
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else
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return pci_ecam_map_bus(bus, devfn, where);
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}
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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static int hisi_pcie_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct acpi_device *adev = to_acpi_device(dev);
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struct acpi_pci_root *root = acpi_driver_data(adev);
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struct resource *res;
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void __iomem *reg_base;
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int ret;
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/*
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* Retrieve RC base and size from a HISI0081 device with _UID
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* matching our segment.
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*/
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res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
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if (!res)
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return -ENOMEM;
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ret = acpi_get_rc_resources(dev, "HISI0081", root->segment, res);
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if (ret) {
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dev_err(dev, "can't get rc base address\n");
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return -ENOMEM;
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}
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reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
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if (!reg_base)
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return -ENOMEM;
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cfg->priv = reg_base;
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return 0;
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}
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struct pci_ecam_ops hisi_pcie_ops = {
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.bus_shift = 20,
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.init = hisi_pcie_init,
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.pci_ops = {
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.map_bus = hisi_pcie_map_bus,
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.read = hisi_pcie_rd_conf,
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.write = hisi_pcie_wr_conf,
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}
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};
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#endif
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#ifdef CONFIG_PCI_HISI
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#include "pcie-designware.h"
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#define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818
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#define PCIE_HIP06_CTRL_OFF 0x1000
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#define PCIE_SYS_STATE4 (PCIE_HIP06_CTRL_OFF + 0x31c)
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#define PCIE_LTSSM_LINKUP_STATE 0x11
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#define PCIE_LTSSM_STATE_MASK 0x3F
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#define to_hisi_pcie(x) dev_get_drvdata((x)->dev)
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struct hisi_pcie;
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struct pcie_soc_ops {
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int (*hisi_pcie_link_up)(struct hisi_pcie *hisi_pcie);
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};
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struct hisi_pcie {
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struct dw_pcie *pci;
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struct regmap *subctrl;
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u32 port_id;
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const struct pcie_soc_ops *soc_ops;
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};
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/* HipXX PCIe host only supports 32-bit config access */
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static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
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u32 *val)
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{
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u32 reg;
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u32 reg_val;
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void *walker = ®_val;
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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walker += (where & 0x3);
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reg = where & ~0x3;
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reg_val = dw_pcie_readl_dbi(pci, reg);
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if (size == 1)
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*val = *(u8 __force *) walker;
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else if (size == 2)
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*val = *(u16 __force *) walker;
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else if (size == 4)
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*val = reg_val;
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else
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_SUCCESSFUL;
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}
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/* HipXX PCIe host only supports 32-bit config access */
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static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
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u32 val)
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{
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u32 reg_val;
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u32 reg;
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void *walker = ®_val;
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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walker += (where & 0x3);
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reg = where & ~0x3;
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if (size == 4)
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dw_pcie_writel_dbi(pci, reg, val);
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else if (size == 2) {
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reg_val = dw_pcie_readl_dbi(pci, reg);
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*(u16 __force *) walker = val;
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dw_pcie_writel_dbi(pci, reg, reg_val);
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} else if (size == 1) {
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reg_val = dw_pcie_readl_dbi(pci, reg);
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*(u8 __force *) walker = val;
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dw_pcie_writel_dbi(pci, reg, reg_val);
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} else
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_SUCCESSFUL;
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}
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static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
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{
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u32 val;
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regmap_read(hisi_pcie->subctrl, PCIE_SUBCTRL_SYS_STATE4_REG +
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0x100 * hisi_pcie->port_id, &val);
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return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
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}
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static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
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{
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struct dw_pcie *pci = hisi_pcie->pci;
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u32 val;
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val = dw_pcie_readl_dbi(pci, PCIE_SYS_STATE4);
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return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
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}
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static int hisi_pcie_link_up(struct dw_pcie *pci)
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{
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struct hisi_pcie *hisi_pcie = to_hisi_pcie(pci);
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return hisi_pcie->soc_ops->hisi_pcie_link_up(hisi_pcie);
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}
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static const struct dw_pcie_host_ops hisi_pcie_host_ops = {
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.rd_own_conf = hisi_pcie_cfg_read,
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.wr_own_conf = hisi_pcie_cfg_write,
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};
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static int hisi_add_pcie_port(struct hisi_pcie *hisi_pcie,
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struct platform_device *pdev)
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{
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struct dw_pcie *pci = hisi_pcie->pci;
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struct pcie_port *pp = &pci->pp;
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struct device *dev = &pdev->dev;
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int ret;
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u32 port_id;
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if (of_property_read_u32(dev->of_node, "port-id", &port_id)) {
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dev_err(dev, "failed to read port-id\n");
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return -EINVAL;
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}
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if (port_id > 3) {
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dev_err(dev, "Invalid port-id: %d\n", port_id);
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return -EINVAL;
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}
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hisi_pcie->port_id = port_id;
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pp->ops = &hisi_pcie_host_ops;
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(dev, "failed to initialize host\n");
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return ret;
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}
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return 0;
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}
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static const struct dw_pcie_ops dw_pcie_ops = {
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.link_up = hisi_pcie_link_up,
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};
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static int hisi_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct dw_pcie *pci;
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struct hisi_pcie *hisi_pcie;
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struct resource *reg;
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int ret;
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hisi_pcie = devm_kzalloc(dev, sizeof(*hisi_pcie), GFP_KERNEL);
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if (!hisi_pcie)
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return -ENOMEM;
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pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
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if (!pci)
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return -ENOMEM;
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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hisi_pcie->pci = pci;
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hisi_pcie->soc_ops = of_device_get_match_data(dev);
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hisi_pcie->subctrl =
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syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
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if (IS_ERR(hisi_pcie->subctrl)) {
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dev_err(dev, "cannot get subctrl base\n");
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return PTR_ERR(hisi_pcie->subctrl);
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}
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reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
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pci->dbi_base = devm_pci_remap_cfg_resource(dev, reg);
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if (IS_ERR(pci->dbi_base))
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return PTR_ERR(pci->dbi_base);
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platform_set_drvdata(pdev, hisi_pcie);
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ret = hisi_add_pcie_port(hisi_pcie, pdev);
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if (ret)
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return ret;
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return 0;
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}
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static struct pcie_soc_ops hip05_ops = {
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&hisi_pcie_link_up_hip05
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};
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static struct pcie_soc_ops hip06_ops = {
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&hisi_pcie_link_up_hip06
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};
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static const struct of_device_id hisi_pcie_of_match[] = {
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{
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.compatible = "hisilicon,hip05-pcie",
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.data = (void *) &hip05_ops,
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},
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{
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.compatible = "hisilicon,hip06-pcie",
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.data = (void *) &hip06_ops,
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},
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{},
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};
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static struct platform_driver hisi_pcie_driver = {
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.probe = hisi_pcie_probe,
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.driver = {
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.name = "hisi-pcie",
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.of_match_table = hisi_pcie_of_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(hisi_pcie_driver);
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static int hisi_pcie_almost_ecam_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct pci_ecam_ops *ops;
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ops = (struct pci_ecam_ops *)of_device_get_match_data(dev);
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return pci_host_common_probe(pdev, ops);
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}
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static int hisi_pcie_platform_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct platform_device *pdev = to_platform_device(dev);
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struct resource *res;
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void __iomem *reg_base;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res) {
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dev_err(dev, "missing \"reg[1]\"property\n");
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return -EINVAL;
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}
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reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
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if (!reg_base)
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return -ENOMEM;
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cfg->priv = reg_base;
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return 0;
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}
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struct pci_ecam_ops hisi_pcie_platform_ops = {
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.bus_shift = 20,
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.init = hisi_pcie_platform_init,
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.pci_ops = {
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.map_bus = hisi_pcie_map_bus,
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.read = hisi_pcie_rd_conf,
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.write = hisi_pcie_wr_conf,
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}
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};
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static const struct of_device_id hisi_pcie_almost_ecam_of_match[] = {
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{
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.compatible = "hisilicon,hip06-pcie-ecam",
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.data = (void *) &hisi_pcie_platform_ops,
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},
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{
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.compatible = "hisilicon,hip07-pcie-ecam",
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.data = (void *) &hisi_pcie_platform_ops,
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},
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{},
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};
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static struct platform_driver hisi_pcie_almost_ecam_driver = {
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.probe = hisi_pcie_almost_ecam_probe,
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.driver = {
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.name = "hisi-pcie-almost-ecam",
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.of_match_table = hisi_pcie_almost_ecam_of_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(hisi_pcie_almost_ecam_driver);
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#endif
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#endif
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