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![Jianguo Sun](/assets/img/avatar_default.png)
Add a HiSilicon STB SoC PCIe controller driver. This controller is based on the DesignWare PCIe core. Signed-off-by: Jianguo Sun <sunjianguo1@huawei.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
470 lines
11 KiB
C
470 lines
11 KiB
C
/*
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* PCIe host controller driver for HiSilicon STB SoCs
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*
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* Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
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*
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* Authors: Ruqiang Ju <juruqiang@hisilicon.com>
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* Jianguo Sun <sunjianguo1@huawei.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include <linux/reset.h>
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#include "pcie-designware.h"
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#define to_histb_pcie(x) dev_get_drvdata((x)->dev)
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#define PCIE_SYS_CTRL0 0x0000
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#define PCIE_SYS_CTRL1 0x0004
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#define PCIE_SYS_CTRL7 0x001C
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#define PCIE_SYS_CTRL13 0x0034
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#define PCIE_SYS_CTRL15 0x003C
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#define PCIE_SYS_CTRL16 0x0040
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#define PCIE_SYS_CTRL17 0x0044
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#define PCIE_SYS_STAT0 0x0100
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#define PCIE_SYS_STAT4 0x0110
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#define PCIE_RDLH_LINK_UP BIT(5)
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#define PCIE_XMLH_LINK_UP BIT(15)
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#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21)
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#define PCIE_APP_LTSSM_ENABLE BIT(11)
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#define PCIE_DEVICE_TYPE_MASK GENMASK(31, 28)
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#define PCIE_WM_EP 0
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#define PCIE_WM_LEGACY BIT(1)
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#define PCIE_WM_RC BIT(30)
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#define PCIE_LTSSM_STATE_MASK GENMASK(5, 0)
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#define PCIE_LTSSM_STATE_ACTIVE 0x11
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struct histb_pcie {
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struct dw_pcie *pci;
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struct clk *aux_clk;
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struct clk *pipe_clk;
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struct clk *sys_clk;
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struct clk *bus_clk;
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struct phy *phy;
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struct reset_control *soft_reset;
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struct reset_control *sys_reset;
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struct reset_control *bus_reset;
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void __iomem *ctrl;
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int reset_gpio;
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};
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static u32 histb_pcie_readl(struct histb_pcie *histb_pcie, u32 reg)
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{
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return readl(histb_pcie->ctrl + reg);
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}
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static void histb_pcie_writel(struct histb_pcie *histb_pcie, u32 reg, u32 val)
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{
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writel(val, histb_pcie->ctrl + reg);
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}
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static void histb_pcie_dbi_w_mode(struct pcie_port *pp, bool enable)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct histb_pcie *hipcie = to_histb_pcie(pci);
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u32 val;
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val = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0);
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if (enable)
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val |= PCIE_ELBI_SLV_DBI_ENABLE;
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else
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val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
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histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, val);
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}
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static void histb_pcie_dbi_r_mode(struct pcie_port *pp, bool enable)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct histb_pcie *hipcie = to_histb_pcie(pci);
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u32 val;
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val = histb_pcie_readl(hipcie, PCIE_SYS_CTRL1);
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if (enable)
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val |= PCIE_ELBI_SLV_DBI_ENABLE;
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else
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val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
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histb_pcie_writel(hipcie, PCIE_SYS_CTRL1, val);
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}
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static u32 histb_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
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u32 reg, size_t size)
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{
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u32 val;
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histb_pcie_dbi_r_mode(&pci->pp, true);
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dw_pcie_read(base + reg, size, &val);
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histb_pcie_dbi_r_mode(&pci->pp, false);
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return val;
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}
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static void histb_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
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u32 reg, size_t size, u32 val)
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{
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histb_pcie_dbi_w_mode(&pci->pp, true);
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dw_pcie_write(base + reg, size, val);
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histb_pcie_dbi_w_mode(&pci->pp, false);
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}
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static int histb_pcie_rd_own_conf(struct pcie_port *pp, int where,
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int size, u32 *val)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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int ret;
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histb_pcie_dbi_r_mode(pp, true);
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ret = dw_pcie_read(pci->dbi_base + where, size, val);
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histb_pcie_dbi_r_mode(pp, false);
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return ret;
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}
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static int histb_pcie_wr_own_conf(struct pcie_port *pp, int where,
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int size, u32 val)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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int ret;
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histb_pcie_dbi_w_mode(pp, true);
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ret = dw_pcie_write(pci->dbi_base + where, size, val);
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histb_pcie_dbi_w_mode(pp, false);
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return ret;
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}
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static int histb_pcie_link_up(struct dw_pcie *pci)
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{
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struct histb_pcie *hipcie = to_histb_pcie(pci);
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u32 regval;
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u32 status;
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regval = histb_pcie_readl(hipcie, PCIE_SYS_STAT0);
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status = histb_pcie_readl(hipcie, PCIE_SYS_STAT4);
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status &= PCIE_LTSSM_STATE_MASK;
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if ((regval & PCIE_XMLH_LINK_UP) && (regval & PCIE_RDLH_LINK_UP) &&
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(status == PCIE_LTSSM_STATE_ACTIVE))
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return 1;
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return 0;
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}
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static int histb_pcie_establish_link(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct histb_pcie *hipcie = to_histb_pcie(pci);
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u32 regval;
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if (dw_pcie_link_up(pci)) {
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dev_info(pci->dev, "Link already up\n");
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return 0;
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}
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/* PCIe RC work mode */
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regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0);
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regval &= ~PCIE_DEVICE_TYPE_MASK;
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regval |= PCIE_WM_RC;
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histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, regval);
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/* setup root complex */
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dw_pcie_setup_rc(pp);
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/* assert LTSSM enable */
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regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL7);
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regval |= PCIE_APP_LTSSM_ENABLE;
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histb_pcie_writel(hipcie, PCIE_SYS_CTRL7, regval);
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return dw_pcie_wait_for_link(pci);
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}
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static int histb_pcie_host_init(struct pcie_port *pp)
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{
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histb_pcie_establish_link(pp);
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if (IS_ENABLED(CONFIG_PCI_MSI))
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dw_pcie_msi_init(pp);
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return 0;
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}
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static struct dw_pcie_host_ops histb_pcie_host_ops = {
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.rd_own_conf = histb_pcie_rd_own_conf,
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.wr_own_conf = histb_pcie_wr_own_conf,
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.host_init = histb_pcie_host_init,
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};
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static irqreturn_t histb_pcie_msi_irq_handler(int irq, void *arg)
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{
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struct pcie_port *pp = arg;
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return dw_handle_msi_irq(pp);
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}
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static void histb_pcie_host_disable(struct histb_pcie *hipcie)
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{
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reset_control_assert(hipcie->soft_reset);
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reset_control_assert(hipcie->sys_reset);
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reset_control_assert(hipcie->bus_reset);
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clk_disable_unprepare(hipcie->aux_clk);
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clk_disable_unprepare(hipcie->pipe_clk);
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clk_disable_unprepare(hipcie->sys_clk);
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clk_disable_unprepare(hipcie->bus_clk);
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if (gpio_is_valid(hipcie->reset_gpio))
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gpio_set_value_cansleep(hipcie->reset_gpio, 0);
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}
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static int histb_pcie_host_enable(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct histb_pcie *hipcie = to_histb_pcie(pci);
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struct device *dev = pci->dev;
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int ret;
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/* power on PCIe device if have */
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if (gpio_is_valid(hipcie->reset_gpio))
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gpio_set_value_cansleep(hipcie->reset_gpio, 1);
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ret = clk_prepare_enable(hipcie->bus_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable bus clk\n");
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goto err_bus_clk;
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}
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ret = clk_prepare_enable(hipcie->sys_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable sys clk\n");
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goto err_sys_clk;
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}
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ret = clk_prepare_enable(hipcie->pipe_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable pipe clk\n");
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goto err_pipe_clk;
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}
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ret = clk_prepare_enable(hipcie->aux_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable aux clk\n");
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goto err_aux_clk;
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}
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reset_control_assert(hipcie->soft_reset);
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reset_control_deassert(hipcie->soft_reset);
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reset_control_assert(hipcie->sys_reset);
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reset_control_deassert(hipcie->sys_reset);
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reset_control_assert(hipcie->bus_reset);
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reset_control_deassert(hipcie->bus_reset);
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return 0;
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err_aux_clk:
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clk_disable_unprepare(hipcie->aux_clk);
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err_pipe_clk:
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clk_disable_unprepare(hipcie->pipe_clk);
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err_sys_clk:
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clk_disable_unprepare(hipcie->sys_clk);
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err_bus_clk:
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clk_disable_unprepare(hipcie->bus_clk);
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return ret;
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}
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static const struct dw_pcie_ops dw_pcie_ops = {
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.read_dbi = histb_pcie_read_dbi,
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.write_dbi = histb_pcie_write_dbi,
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.link_up = histb_pcie_link_up,
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};
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static int histb_pcie_probe(struct platform_device *pdev)
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{
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struct histb_pcie *hipcie;
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struct dw_pcie *pci;
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struct pcie_port *pp;
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struct resource *res;
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struct device_node *np = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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enum of_gpio_flags of_flags;
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unsigned long flag = GPIOF_DIR_OUT;
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int ret;
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hipcie = devm_kzalloc(dev, sizeof(*hipcie), GFP_KERNEL);
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if (!hipcie)
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return -ENOMEM;
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pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
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if (!pci)
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return -ENOMEM;
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hipcie->pci = pci;
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pp = &pci->pp;
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control");
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hipcie->ctrl = devm_ioremap_resource(dev, res);
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if (IS_ERR(hipcie->ctrl)) {
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dev_err(dev, "cannot get control reg base\n");
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return PTR_ERR(hipcie->ctrl);
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc-dbi");
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pci->dbi_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(pci->dbi_base)) {
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dev_err(dev, "cannot get rc-dbi base\n");
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return PTR_ERR(pci->dbi_base);
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}
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hipcie->reset_gpio = of_get_named_gpio_flags(np,
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"reset-gpios", 0, &of_flags);
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if (of_flags & OF_GPIO_ACTIVE_LOW)
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flag |= GPIOF_ACTIVE_LOW;
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if (gpio_is_valid(hipcie->reset_gpio)) {
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ret = devm_gpio_request_one(dev, hipcie->reset_gpio,
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flag, "PCIe device power control");
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if (ret) {
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dev_err(dev, "unable to request gpio\n");
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return ret;
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}
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}
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hipcie->aux_clk = devm_clk_get(dev, "aux");
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if (IS_ERR(hipcie->aux_clk)) {
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dev_err(dev, "Failed to get PCIe aux clk\n");
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return PTR_ERR(hipcie->aux_clk);
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}
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hipcie->pipe_clk = devm_clk_get(dev, "pipe");
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if (IS_ERR(hipcie->pipe_clk)) {
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dev_err(dev, "Failed to get PCIe pipe clk\n");
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return PTR_ERR(hipcie->pipe_clk);
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}
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hipcie->sys_clk = devm_clk_get(dev, "sys");
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if (IS_ERR(hipcie->sys_clk)) {
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dev_err(dev, "Failed to get PCIEe sys clk\n");
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return PTR_ERR(hipcie->sys_clk);
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}
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hipcie->bus_clk = devm_clk_get(dev, "bus");
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if (IS_ERR(hipcie->bus_clk)) {
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dev_err(dev, "Failed to get PCIe bus clk\n");
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return PTR_ERR(hipcie->bus_clk);
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}
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hipcie->soft_reset = devm_reset_control_get(dev, "soft");
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if (IS_ERR(hipcie->soft_reset)) {
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dev_err(dev, "couldn't get soft reset\n");
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return PTR_ERR(hipcie->soft_reset);
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}
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hipcie->sys_reset = devm_reset_control_get(dev, "sys");
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if (IS_ERR(hipcie->sys_reset)) {
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dev_err(dev, "couldn't get sys reset\n");
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return PTR_ERR(hipcie->sys_reset);
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}
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hipcie->bus_reset = devm_reset_control_get(dev, "bus");
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if (IS_ERR(hipcie->bus_reset)) {
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dev_err(dev, "couldn't get bus reset\n");
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return PTR_ERR(hipcie->bus_reset);
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}
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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pp->msi_irq = platform_get_irq_byname(pdev, "msi");
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if (pp->msi_irq < 0) {
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dev_err(dev, "Failed to get MSI IRQ\n");
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return pp->msi_irq;
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}
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ret = devm_request_irq(dev, pp->msi_irq,
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histb_pcie_msi_irq_handler,
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IRQF_SHARED, "histb-pcie-msi", pp);
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if (ret) {
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dev_err(dev, "cannot request MSI IRQ\n");
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return ret;
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}
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}
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hipcie->phy = devm_phy_get(dev, "phy");
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if (IS_ERR(hipcie->phy)) {
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dev_info(dev, "no pcie-phy found\n");
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hipcie->phy = NULL;
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/* fall through here!
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* if no pcie-phy found, phy init
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* should be done under boot!
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*/
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} else {
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phy_init(hipcie->phy);
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}
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pp->root_bus_nr = -1;
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pp->ops = &histb_pcie_host_ops;
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platform_set_drvdata(pdev, hipcie);
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ret = histb_pcie_host_enable(pp);
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if (ret) {
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dev_err(dev, "failed to enable host\n");
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return ret;
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}
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(dev, "failed to initialize host\n");
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return ret;
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}
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return 0;
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}
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static int histb_pcie_remove(struct platform_device *pdev)
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{
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struct histb_pcie *hipcie = platform_get_drvdata(pdev);
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histb_pcie_host_disable(hipcie);
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if (hipcie->phy)
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phy_exit(hipcie->phy);
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return 0;
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}
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static const struct of_device_id histb_pcie_of_match[] = {
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{ .compatible = "hisilicon,hi3798cv200-pcie", },
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{},
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};
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MODULE_DEVICE_TABLE(of, histb_pcie_of_match);
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static struct platform_driver histb_pcie_platform_driver = {
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.probe = histb_pcie_probe,
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.remove = histb_pcie_remove,
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.driver = {
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.name = "histb-pcie",
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.of_match_table = histb_pcie_of_match,
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},
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};
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module_platform_driver(histb_pcie_platform_driver);
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MODULE_DESCRIPTION("HiSilicon STB PCIe host controller driver");
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MODULE_LICENSE("GPL v2");
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