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33e5b5746c
When the last VM is terminated, the host kernel will invoke function
hardware_disable_nolock() on each CPU to disable the related virtualization
functions. Here, RISC-V currently only clears hideleg CSR and hedeleg CSR.
This behavior will cause the host kernel to receive spurious interrupts if
hvip CSR has pending interrupts and the corresponding enable bits in vsie
CSR are asserted. To avoid it, hvip CSR and vsie CSR must be cleared
before clearing hideleg CSR.
Fixes: 99cdc6c18c ("RISC-V: Add initial skeletal KVM support")
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
126 lines
2.5 KiB
C
126 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/kvm_host.h>
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#include <asm/csr.h>
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#include <asm/hwcap.h>
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#include <asm/sbi.h>
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long kvm_arch_dev_ioctl(struct file *filp,
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unsigned int ioctl, unsigned long arg)
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{
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return -EINVAL;
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}
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int kvm_arch_check_processor_compat(void *opaque)
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{
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return 0;
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}
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int kvm_arch_hardware_setup(void *opaque)
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{
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return 0;
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}
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int kvm_arch_hardware_enable(void)
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{
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unsigned long hideleg, hedeleg;
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hedeleg = 0;
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hedeleg |= (1UL << EXC_INST_MISALIGNED);
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hedeleg |= (1UL << EXC_BREAKPOINT);
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hedeleg |= (1UL << EXC_SYSCALL);
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hedeleg |= (1UL << EXC_INST_PAGE_FAULT);
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hedeleg |= (1UL << EXC_LOAD_PAGE_FAULT);
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hedeleg |= (1UL << EXC_STORE_PAGE_FAULT);
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csr_write(CSR_HEDELEG, hedeleg);
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hideleg = 0;
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hideleg |= (1UL << IRQ_VS_SOFT);
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hideleg |= (1UL << IRQ_VS_TIMER);
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hideleg |= (1UL << IRQ_VS_EXT);
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csr_write(CSR_HIDELEG, hideleg);
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csr_write(CSR_HCOUNTEREN, -1UL);
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csr_write(CSR_HVIP, 0);
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return 0;
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}
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void kvm_arch_hardware_disable(void)
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{
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/*
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* After clearing the hideleg CSR, the host kernel will receive
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* spurious interrupts if hvip CSR has pending interrupts and the
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* corresponding enable bits in vsie CSR are asserted. To avoid it,
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* hvip CSR and vsie CSR must be cleared before clearing hideleg CSR.
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*/
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csr_write(CSR_VSIE, 0);
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csr_write(CSR_HVIP, 0);
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csr_write(CSR_HEDELEG, 0);
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csr_write(CSR_HIDELEG, 0);
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}
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int kvm_arch_init(void *opaque)
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{
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const char *str;
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if (!riscv_isa_extension_available(NULL, h)) {
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kvm_info("hypervisor extension not available\n");
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return -ENODEV;
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}
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if (sbi_spec_is_0_1()) {
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kvm_info("require SBI v0.2 or higher\n");
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return -ENODEV;
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}
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if (sbi_probe_extension(SBI_EXT_RFENCE) <= 0) {
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kvm_info("require SBI RFENCE extension\n");
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return -ENODEV;
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}
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kvm_riscv_stage2_mode_detect();
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kvm_riscv_stage2_vmid_detect();
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kvm_info("hypervisor extension available\n");
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switch (kvm_riscv_stage2_mode()) {
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case HGATP_MODE_SV32X4:
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str = "Sv32x4";
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break;
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case HGATP_MODE_SV39X4:
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str = "Sv39x4";
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break;
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case HGATP_MODE_SV48X4:
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str = "Sv48x4";
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break;
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default:
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return -ENODEV;
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}
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kvm_info("using %s G-stage page table format\n", str);
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kvm_info("VMID %ld bits available\n", kvm_riscv_stage2_vmid_bits());
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return 0;
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}
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void kvm_arch_exit(void)
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{
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}
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static int riscv_kvm_init(void)
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{
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return kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
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}
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module_init(riscv_kvm_init);
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