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3f0cdb9454
The SPLL2 on iMX8ULP is different with other frac PLLs, it can
support VCO from 650Mhz to 1Ghz. According to RM, the MULT is
using a range from 27 to 54, not some fixed values. If using
current PLL implementation, some clock rate can't be supported.
Fix the issue by adding new type for the SPLL2 and use MULT range
to replace MULT table
Fixes: 5f0601c47c ("clk: imx: Update the pllv4 to support imx8ulp")
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230625123340.4067536-1-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
486 lines
17 KiB
C
486 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __MACH_IMX_CLK_H
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#define __MACH_IMX_CLK_H
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#include <linux/bits.h>
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#include <linux/spinlock.h>
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#include <linux/clk-provider.h>
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extern spinlock_t imx_ccm_lock;
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extern bool mcore_booted;
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void imx_check_clocks(struct clk *clks[], unsigned int count);
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void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
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#ifndef MODULE
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void imx_register_uart_clocks(void);
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#else
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static inline void imx_register_uart_clocks(void)
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{
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}
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#endif
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void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
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void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count);
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extern void imx_cscmr1_fixup(u32 *val);
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enum imx_pllv1_type {
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IMX_PLLV1_IMX1,
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IMX_PLLV1_IMX21,
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IMX_PLLV1_IMX25,
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IMX_PLLV1_IMX27,
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IMX_PLLV1_IMX31,
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IMX_PLLV1_IMX35,
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};
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enum imx_sscg_pll_type {
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SCCG_PLL1,
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SCCG_PLL2,
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};
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enum imx_pll14xx_type {
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PLL_1416X,
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PLL_1443X,
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};
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enum imx_pllv4_type {
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IMX_PLLV4_IMX7ULP,
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IMX_PLLV4_IMX8ULP,
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IMX_PLLV4_IMX8ULP_1GHZ,
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};
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enum imx_pfdv2_type {
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IMX_PFDV2_IMX7ULP,
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IMX_PFDV2_IMX8ULP,
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};
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/* NOTE: Rate table should be kept sorted in descending order. */
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struct imx_pll14xx_rate_table {
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unsigned int rate;
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unsigned int pdiv;
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unsigned int mdiv;
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unsigned int sdiv;
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unsigned int kdiv;
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};
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struct imx_pll14xx_clk {
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enum imx_pll14xx_type type;
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const struct imx_pll14xx_rate_table *rate_table;
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int rate_count;
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int flags;
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};
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extern struct imx_pll14xx_clk imx_1416x_pll;
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extern struct imx_pll14xx_clk imx_1443x_pll;
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extern struct imx_pll14xx_clk imx_1443x_dram_pll;
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#define CLK_FRACN_GPPLL_INTEGER BIT(0)
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#define CLK_FRACN_GPPLL_FRACN BIT(1)
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/* NOTE: Rate table should be kept sorted in descending order. */
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struct imx_fracn_gppll_rate_table {
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unsigned int rate;
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unsigned int mfi;
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unsigned int mfn;
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unsigned int mfd;
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unsigned int rdiv;
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unsigned int odiv;
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};
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struct imx_fracn_gppll_clk {
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const struct imx_fracn_gppll_rate_table *rate_table;
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int rate_count;
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int flags;
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};
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struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base,
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const struct imx_fracn_gppll_clk *pll_clk);
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struct clk_hw *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name,
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void __iomem *base,
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const struct imx_fracn_gppll_clk *pll_clk);
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extern struct imx_fracn_gppll_clk imx_fracn_gppll;
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extern struct imx_fracn_gppll_clk imx_fracn_gppll_integer;
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#define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
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to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
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#define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
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cgr_val, cgr_mask, clk_gate_flags, lock, share_count) \
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to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
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cgr_val, cgr_mask, clk_gate_flags, lock, share_count))
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#define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
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to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
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#define imx_clk_pfd(name, parent_name, reg, idx) \
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to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
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#define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
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to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
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#define imx_clk_fixed(name, rate) \
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to_clk(imx_clk_hw_fixed(name, rate))
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#define imx_clk_fixed_factor(name, parent, mult, div) \
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to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
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#define imx_clk_divider(name, parent, reg, shift, width) \
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to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
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#define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \
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to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
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#define imx_clk_gate(name, parent, reg, shift) \
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to_clk(imx_clk_hw_gate(name, parent, reg, shift))
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#define imx_clk_gate_dis(name, parent, reg, shift) \
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to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
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#define imx_clk_gate2(name, parent, reg, shift) \
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to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
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#define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \
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to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL))
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#define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
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to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
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#define imx_clk_mux(name, reg, shift, width, parents, num_parents) \
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to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
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#define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
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to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
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#define imx_clk_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \
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to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags))
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#define imx_clk_pllv1(type, name, parent, base) \
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to_clk(imx_clk_hw_pllv1(type, name, parent, base))
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#define imx_clk_pllv2(name, parent, base) \
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to_clk(imx_clk_hw_pllv2(name, parent, base))
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#define imx_clk_hw_gate(name, parent, reg, shift) \
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imx_clk_hw_gate_flags(name, parent, reg, shift, 0)
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#define imx_clk_hw_gate2(name, parent, reg, shift) \
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imx_clk_hw_gate2_flags(name, parent, reg, shift, 0)
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#define imx_clk_hw_gate_dis(name, parent, reg, shift) \
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imx_clk_hw_gate_dis_flags(name, parent, reg, shift, 0)
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#define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \
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__imx_clk_hw_gate(name, parent, reg, shift, flags, CLK_GATE_SET_TO_DISABLE)
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#define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \
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__imx_clk_hw_gate(name, parent, reg, shift, flags, 0)
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#define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \
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__imx_clk_hw_gate2(name, parent, reg, shift, 0x3, flags, NULL)
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#define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \
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__imx_clk_hw_gate2(name, parent, reg, shift, 0x3, 0, shared_count)
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#define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \
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__imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count)
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#define imx_clk_hw_gate3(name, parent, reg, shift) \
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imx_clk_hw_gate3_flags(name, parent, reg, shift, 0)
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#define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \
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__imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0)
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#define imx_clk_hw_gate4(name, parent, reg, shift) \
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imx_clk_hw_gate4_flags(name, parent, reg, shift, 0)
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#define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) \
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imx_clk_hw_gate2_flags(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE)
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#define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \
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imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, 0)
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#define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \
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__imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, 0, 0)
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#define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
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__imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags, 0)
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#define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \
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__imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY)
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#define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \
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__imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags | CLK_OPS_PARENT_ENABLE, 0)
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#define imx_clk_hw_divider(name, parent, reg, shift, width) \
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__imx_clk_hw_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT)
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#define imx_clk_hw_divider2(name, parent, reg, shift, width) \
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__imx_clk_hw_divider(name, parent, reg, shift, width, \
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CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE)
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#define imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags) \
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__imx_clk_hw_divider(name, parent, reg, shift, width, flags)
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#define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \
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imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk)
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struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
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const char *parent_name, void __iomem *base,
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const struct imx_pll14xx_clk *pll_clk);
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struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
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const char *parent, void __iomem *base);
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struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
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void __iomem *base);
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struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
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void __iomem *base);
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struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
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const char * const *parent_names,
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u8 num_parents,
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u8 parent, u8 bypass1, u8 bypass2,
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void __iomem *base,
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unsigned long flags);
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enum imx_pllv3_type {
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IMX_PLLV3_GENERIC,
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IMX_PLLV3_SYS,
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IMX_PLLV3_USB,
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IMX_PLLV3_USB_VF610,
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IMX_PLLV3_AV,
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IMX_PLLV3_ENET,
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IMX_PLLV3_ENET_IMX7,
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IMX_PLLV3_SYS_VF610,
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IMX_PLLV3_DDR_IMX7,
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IMX_PLLV3_AV_IMX7,
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};
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struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent_name, void __iomem *base, u32 div_mask);
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#define PLL_1416X_RATE(_rate, _m, _p, _s) \
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{ \
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.rate = (_rate), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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}
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#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
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{ \
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.rate = (_rate), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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.kdiv = (_k), \
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}
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struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name,
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const char *parent_name, void __iomem *base);
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struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask,
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u8 clk_gate_flags, spinlock_t *lock,
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unsigned int *share_count);
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struct clk * imx_obtain_fixed_clock(
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const char *name, unsigned long rate);
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struct clk_hw *imx_obtain_fixed_clock_hw(
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const char *name, unsigned long rate);
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struct clk_hw *imx_obtain_fixed_of_clock(struct device_node *np,
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const char *name, unsigned long rate);
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struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name);
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struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u32 exclusive_mask);
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struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
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void __iomem *reg, u8 idx);
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struct clk_hw *imx_clk_hw_pfdv2(enum imx_pfdv2_type type, const char *name,
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const char *parent_name, void __iomem *reg, u8 idx);
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struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
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void __iomem *reg, u8 shift, u8 width,
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void __iomem *busy_reg, u8 busy_shift);
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struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
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u8 width, void __iomem *busy_reg, u8 busy_shift,
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const char * const *parent_names, int num_parents);
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struct clk_hw *imx7ulp_clk_hw_composite(const char *name,
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const char * const *parent_names,
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int num_parents, bool mux_present,
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bool rate_present, bool gate_present,
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void __iomem *reg);
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struct clk_hw *imx8ulp_clk_hw_composite(const char *name,
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const char * const *parent_names,
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int num_parents, bool mux_present,
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bool rate_present, bool gate_present,
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void __iomem *reg, bool has_swrst);
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struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width,
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void (*fixup)(u32 *val));
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struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char * const *parents,
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int num_parents, void (*fixup)(u32 *val));
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static inline struct clk *to_clk(struct clk_hw *hw)
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{
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if (IS_ERR_OR_NULL(hw))
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return ERR_CAST(hw);
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return hw->clk;
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}
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static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
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{
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return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
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}
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static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name,
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const char *parent, unsigned int mult, unsigned int div)
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{
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return clk_hw_register_fixed_factor(NULL, name, parent,
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CLK_SET_RATE_PARENT, mult, div);
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}
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static inline struct clk_hw *imx_clk_hw_divider_closest(const char *name,
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const char *parent,
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void __iomem *reg, u8 shift,
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u8 width)
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{
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return clk_hw_register_divider(NULL, name, parent, 0,
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reg, shift, width, CLK_DIVIDER_ROUND_CLOSEST, &imx_ccm_lock);
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}
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static inline struct clk_hw *__imx_clk_hw_divider(const char *name,
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const char *parent,
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void __iomem *reg, u8 shift,
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u8 width, unsigned long flags)
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{
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return clk_hw_register_divider(NULL, name, parent, flags,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk_hw *__imx_clk_hw_gate(const char *name, const char *parent,
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void __iomem *reg, u8 shift,
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unsigned long flags,
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unsigned long clk_gate_flags)
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{
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return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
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shift, clk_gate_flags, &imx_ccm_lock);
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}
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static inline struct clk_hw *__imx_clk_hw_gate2(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 cgr_val,
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unsigned long flags,
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unsigned int *share_count)
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{
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return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
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shift, cgr_val, 0x3, 0, &imx_ccm_lock, share_count);
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}
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static inline struct clk_hw *__imx_clk_hw_mux(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char * const *parents,
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int num_parents, unsigned long flags, unsigned long clk_mux_flags)
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{
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return clk_hw_register_mux(NULL, name, parents, num_parents,
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flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
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width, clk_mux_flags, &imx_ccm_lock);
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}
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struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
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struct clk *div, struct clk *mux, struct clk *pll,
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struct clk *step);
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#define IMX_COMPOSITE_CORE BIT(0)
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#define IMX_COMPOSITE_BUS BIT(1)
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#define IMX_COMPOSITE_FW_MANAGED BIT(2)
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#define IMX_COMPOSITE_CLK_FLAGS_DEFAULT \
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(CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
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#define IMX_COMPOSITE_CLK_FLAGS_CRITICAL \
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(IMX_COMPOSITE_CLK_FLAGS_DEFAULT | CLK_IS_CRITICAL)
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#define IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE \
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(IMX_COMPOSITE_CLK_FLAGS_DEFAULT | CLK_GET_RATE_NOCACHE)
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#define IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE \
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(IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE | CLK_IS_CRITICAL)
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struct clk_hw *__imx8m_clk_hw_composite(const char *name,
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const char * const *parent_names,
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int num_parents,
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void __iomem *reg,
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u32 composite_flags,
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unsigned long flags);
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#define _imx8m_clk_hw_composite(name, parent_names, reg, composite_flags, flags) \
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__imx8m_clk_hw_composite(name, parent_names, \
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ARRAY_SIZE(parent_names), reg, composite_flags, flags)
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#define imx8m_clk_hw_composite(name, parent_names, reg) \
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_imx8m_clk_hw_composite(name, parent_names, reg, \
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0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
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#define imx8m_clk_hw_composite_flags(name, parent_names, reg, flags) \
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_imx8m_clk_hw_composite(name, parent_names, reg, \
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0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT | flags)
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#define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
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_imx8m_clk_hw_composite(name, parent_names, reg, \
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0, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
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#define imx8m_clk_hw_composite_bus(name, parent_names, reg) \
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_imx8m_clk_hw_composite(name, parent_names, reg, \
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IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
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#define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \
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_imx8m_clk_hw_composite(name, parent_names, reg, \
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IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
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#define imx8m_clk_hw_composite_core(name, parent_names, reg) \
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_imx8m_clk_hw_composite(name, parent_names, reg, \
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IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
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#define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \
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_imx8m_clk_hw_composite(name, parent_names, reg, \
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IMX_COMPOSITE_FW_MANAGED, \
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IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE)
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#define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \
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_imx8m_clk_hw_composite(name, parent_names, reg, \
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IMX_COMPOSITE_FW_MANAGED, \
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IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE)
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struct clk_hw *imx93_clk_composite_flags(const char *name,
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const char * const *parent_names,
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int num_parents,
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void __iomem *reg,
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u32 domain_id,
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unsigned long flags);
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#define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) \
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imx93_clk_composite_flags(name, parent_names, num_parents, reg, domain_id \
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CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
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struct clk_hw *imx93_clk_gate(struct device *dev, const char *name, const char *parent_name,
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unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val,
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u32 mask, u32 domain_id, unsigned int *share_count);
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struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,
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unsigned long flags, void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, const struct clk_div_table *table,
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spinlock_t *lock);
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struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible,
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u32 reg, const char **parent_names,
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u8 num_parents, const u32 *mux_table, u32 mask);
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#endif
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