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48b16180d0
If we do nothing in suspend/resume, some platform PCIe ip-block can't guarantee the link back to L0 state from sleep, then, when we read the EP device will hang. Only we send pme turnoff message in pci controller suspend, and send pme exit message in resume, the link state will be normal. When we send pme turnoff message in pci controller suspend, the links will into l2/l3 ready, then, host cannot communicate with ep device, but pci-driver will call back EP device to save them state. So we need to change platform_driver->suspend/resume to syscore->suspend/resume. So the new suspend/resume implementation, send pme turnoff message in suspend, and send pme exit message in resume. And add a PME handler, to response PME & message interrupt. Change platform_driver->suspend/resume to syscore->suspend/resume. pci-driver will call back EP device, to save EP state in pci_pm_suspend_noirq, so we need to keep the link, until pci_pm_suspend_noirq finish. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
75 lines
2 KiB
C
75 lines
2 KiB
C
/*
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* Paravirt target for a generic QEMU e500 machine
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*
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* This is intended to be a flexible device-tree-driven platform, not fixed
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* to a particular piece of hardware or a particular spec of virtual hardware,
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* beyond the assumption of an e500-family CPU. Some things are still hardcoded
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* here, such as MPIC, but this is a limitation of the current code rather than
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* an interface contract with QEMU.
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*
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* Copyright 2012 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/of_fdt.h>
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#include <asm/machdep.h>
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#include <asm/time.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include "smp.h"
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#include "mpc85xx.h"
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void __init qemu_e500_pic_init(void)
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{
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struct mpic *mpic;
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unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
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MPIC_ENABLE_COREINT;
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mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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mpic_init(mpic);
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}
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static void __init qemu_e500_setup_arch(void)
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{
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ppc_md.progress("qemu_e500_setup_arch()", 0);
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fsl_pci_assign_primary();
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swiotlb_detect_4g();
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mpc85xx_smp_init();
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}
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init qemu_e500_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return !!of_flat_dt_is_compatible(root, "fsl,qemu-e500");
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}
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machine_arch_initcall(qemu_e500, mpc85xx_common_publish_devices);
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define_machine(qemu_e500) {
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.name = "QEMU e500",
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.probe = qemu_e500_probe,
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.setup_arch = qemu_e500_setup_arch,
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.init_IRQ = qemu_e500_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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.get_irq = mpic_get_coreint_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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