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4df24fef09
Instead of a flow control selection mechanism specifically for 8250, make this available for all debug UARTs. If the debug UART supports waiting for CTS to be asserted, then this code can be activated for terminals that need it. We keep the defaults for EBSA110, Footbridge, Gemini and RPC so that this still works as expected for these older platforms: they assume that flow control shall be enabled for debug prints. I switch the location of the check for ifdef CONFIG_DEBUG_UART_FLOW_CONTROL from the actual debug UART drivers: the code would get compiled-out for 8250 and Tegra unless their custom config (or passing -DFLOW_CONTROL in the Tegra case) was not set. Instead this is conditional at the three places where we print debug messages. The idea is that debug UARTs can be implemented without this ifdef boilerplate so they look cleaner, alas the ifdef has to be somewhere. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
161 lines
2.6 KiB
ArmAsm
161 lines
2.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* linux/arch/arm/kernel/debug.S
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*
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* Copyright (C) 1994-1999 Russell King
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*
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* 32-bit debugging code
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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.text
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/*
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* Some debugging routines (useful if you've got MM problems and
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* printk isn't working). For DEBUGGING ONLY!!! Do not leave
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* references to these in a production kernel!
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*/
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#if !defined(CONFIG_DEBUG_SEMIHOSTING)
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#include CONFIG_DEBUG_LL_INCLUDE
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#endif
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#ifdef CONFIG_MMU
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.macro addruart_current, rx, tmp1, tmp2
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addruart \tmp1, \tmp2, \rx
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mrc p15, 0, \rx, c1, c0
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tst \rx, #1
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moveq \rx, \tmp1
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movne \rx, \tmp2
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.endm
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#else /* !CONFIG_MMU */
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.macro addruart_current, rx, tmp1, tmp2
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addruart \rx, \tmp1, \tmp2
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.endm
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#endif /* CONFIG_MMU */
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/*
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* Useful debugging routines
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*/
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ENTRY(printhex8)
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mov r1, #8
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b printhex
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ENDPROC(printhex8)
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ENTRY(printhex4)
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mov r1, #4
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b printhex
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ENDPROC(printhex4)
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ENTRY(printhex2)
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mov r1, #2
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printhex: adr r2, hexbuf_rel
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ldr r3, [r2]
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add r2, r2, r3
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add r3, r2, r1
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mov r1, #0
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strb r1, [r3]
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1: and r1, r0, #15
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mov r0, r0, lsr #4
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cmp r1, #10
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addlt r1, r1, #'0'
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addge r1, r1, #'a' - 10
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strb r1, [r3, #-1]!
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teq r3, r2
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bne 1b
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mov r0, r2
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b printascii
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ENDPROC(printhex2)
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.pushsection .bss
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hexbuf_addr: .space 16
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.popsection
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.align
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hexbuf_rel: .long hexbuf_addr - .
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.ltorg
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#ifndef CONFIG_DEBUG_SEMIHOSTING
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ENTRY(printascii)
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addruart_current r3, r1, r2
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1: teq r0, #0
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ldrbne r1, [r0], #1
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teqne r1, #0
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reteq lr
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2: teq r1, #'\n'
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bne 3f
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mov r1, #'\r'
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#ifdef CONFIG_DEBUG_UART_FLOW_CONTROL
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waituartcts r2, r3
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#endif
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waituarttxrdy r2, r3
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senduart r1, r3
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busyuart r2, r3
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mov r1, #'\n'
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3:
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#ifdef CONFIG_DEBUG_UART_FLOW_CONTROL
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waituartcts r2, r3
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#endif
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waituarttxrdy r2, r3
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senduart r1, r3
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busyuart r2, r3
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b 1b
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ENDPROC(printascii)
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ENTRY(printch)
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addruart_current r3, r1, r2
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mov r1, r0
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mov r0, #0
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b 2b
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ENDPROC(printch)
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#ifdef CONFIG_MMU
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ENTRY(debug_ll_addr)
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addruart r2, r3, ip
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str r2, [r0]
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str r3, [r1]
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ret lr
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ENDPROC(debug_ll_addr)
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#endif
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#else
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ENTRY(printascii)
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mov r1, r0
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mov r0, #0x04 @ SYS_WRITE0
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ARM( svc #0x123456 )
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#ifdef CONFIG_CPU_V7M
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THUMB( bkpt #0xab )
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#else
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THUMB( svc #0xab )
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#endif
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ret lr
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ENDPROC(printascii)
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ENTRY(printch)
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adr r1, hexbuf_rel
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ldr r2, [r1]
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add r1, r1, r2
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strb r0, [r1]
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mov r0, #0x03 @ SYS_WRITEC
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ARM( svc #0x123456 )
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#ifdef CONFIG_CPU_V7M
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THUMB( bkpt #0xab )
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#else
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THUMB( svc #0xab )
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#endif
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ret lr
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ENDPROC(printch)
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ENTRY(debug_ll_addr)
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mov r2, #0
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str r2, [r0]
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str r2, [r1]
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ret lr
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ENDPROC(debug_ll_addr)
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#endif
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