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5919eec0f0
This patch adds SMP support for MStar/Sigmastar chips that have a second core like those in the infinity2m family. So far only single and dual core chips have been found so this does the bare minimum to boot the second core. From what I can tell not having the "holding pen" code to handle multiple cores is fine if there is only one core the will get booted. This might need to be reconsidered if chips with more cores turn up. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Link: https://lore.kernel.org/r/20201201134330.3037007-11-daniel@0x0f.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
129 lines
3.5 KiB
C
129 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree support for MStar/Sigmastar Armv7 SoCs
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*
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* Copyright (c) 2020 thingy.jp
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* Author: Daniel Palmer <daniel@thingy.jp>
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*/
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#include <linux/init.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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/*
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* In the u-boot code the area these registers are in is
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* called "L3 bridge" and there are register descriptions
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* for something in the same area called "AXI".
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*
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* It's not exactly known what this is but the vendor code
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* for both u-boot and linux share calls to "flush the miu pipe".
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* This seems to be to force pending CPU writes to memory so that
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* the state is right before DMA capable devices try to read
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* descriptors and data the CPU has prepared. Without doing this
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* ethernet doesn't work reliably for example.
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*/
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#define MSTARV7_L3BRIDGE_FLUSH 0x14
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#define MSTARV7_L3BRIDGE_STATUS 0x40
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#define MSTARV7_L3BRIDGE_FLUSH_TRIGGER BIT(0)
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#define MSTARV7_L3BRIDGE_STATUS_DONE BIT(12)
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#ifdef CONFIG_SMP
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#define MSTARV7_CPU1_BOOT_ADDR_HIGH 0x4c
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#define MSTARV7_CPU1_BOOT_ADDR_LOW 0x50
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#define MSTARV7_CPU1_UNLOCK 0x58
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#define MSTARV7_CPU1_UNLOCK_MAGIC 0xbabe
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#endif
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static void __iomem *l3bridge;
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static const char * const mstarv7_board_dt_compat[] __initconst = {
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"mstar,infinity",
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"mstar,infinity2m",
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"mstar,infinity3",
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"mstar,mercury5",
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NULL,
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};
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/*
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* This may need locking to deal with situations where an interrupt
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* happens while we are in here and mb() gets called by the interrupt handler.
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*
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* The vendor code did have a spin lock but it doesn't seem to be needed and
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* removing it hasn't caused any side effects so far.
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*
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* [writel|readl]_relaxed have to be used here because otherwise
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* we'd end up right back in here.
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*/
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static void mstarv7_mb(void)
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{
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/* toggle the flush miu pipe fire bit */
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writel_relaxed(0, l3bridge + MSTARV7_L3BRIDGE_FLUSH);
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writel_relaxed(MSTARV7_L3BRIDGE_FLUSH_TRIGGER, l3bridge
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+ MSTARV7_L3BRIDGE_FLUSH);
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while (!(readl_relaxed(l3bridge + MSTARV7_L3BRIDGE_STATUS)
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& MSTARV7_L3BRIDGE_STATUS_DONE)) {
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/* wait for flush to complete */
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}
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}
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#ifdef CONFIG_SMP
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static int mstarv7_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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struct device_node *np;
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u32 bootaddr = (u32) __pa_symbol(secondary_startup_arm);
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void __iomem *smpctrl;
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/*
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* right now we don't know how to boot anything except
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* cpu 1.
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*/
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if (cpu != 1)
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return -EINVAL;
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np = of_find_compatible_node(NULL, NULL, "mstar,smpctrl");
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smpctrl = of_iomap(np, 0);
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if (!smpctrl)
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return -ENODEV;
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/* set the boot address for the second cpu */
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writew(bootaddr & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_LOW);
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writew((bootaddr >> 16) & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_HIGH);
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/* unlock the second cpu */
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writew(MSTARV7_CPU1_UNLOCK_MAGIC, smpctrl + MSTARV7_CPU1_UNLOCK);
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/* and away we go...*/
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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iounmap(smpctrl);
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return 0;
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}
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static const struct smp_operations __initdata mstarv7_smp_ops = {
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.smp_boot_secondary = mstarv7_boot_secondary,
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};
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#endif
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static void __init mstarv7_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "mstar,l3bridge");
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l3bridge = of_iomap(np, 0);
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if (l3bridge)
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soc_mb = mstarv7_mb;
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else
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pr_warn("Failed to install memory barrier, DMA will be broken!\n");
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}
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DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)")
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.dt_compat = mstarv7_board_dt_compat,
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.init_machine = mstarv7_init,
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.smp = smp_ops(mstarv7_smp_ops),
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MACHINE_END
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