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08c619b492
EFCH_PM_DECODEEN3 is supposed to access DECODEEN register bits 24..31,
in other words the register at byte offset 3.
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Fixes: 887d2ec51e ("watchdog: sp5100_tco: Add support for recent FCH versions")
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
Link: https://lore.kernel.org/r/20200910163109.235136-1-linux@roeck-us.net
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
85 lines
2.3 KiB
C
85 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* sp5100_tco: TCO timer driver for sp5100 chipsets.
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*
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* (c) Copyright 2009 Google Inc., All Rights Reserved.
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*
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* TCO timer driver for sp5100 chipsets
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*/
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#include <linux/bitops.h>
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/*
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* Some address definitions for the Watchdog
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*/
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#define SP5100_WDT_MEM_MAP_SIZE 0x08
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#define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */
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#define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */
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#define SP5100_WDT_START_STOP_BIT BIT(0)
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#define SP5100_WDT_FIRED BIT(1)
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#define SP5100_WDT_ACTION_RESET BIT(2)
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#define SP5100_WDT_DISABLED BIT(3)
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#define SP5100_WDT_TRIGGER_BIT BIT(7)
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#define SP5100_PM_IOPORTS_SIZE 0x02
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/*
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* These two IO registers are hardcoded and there doesn't seem to be a way to
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* read them from a register.
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*/
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/* For SP5100/SB7x0/SB8x0 chipset */
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#define SP5100_IO_PM_INDEX_REG 0xCD6
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#define SP5100_IO_PM_DATA_REG 0xCD7
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/* For SP5100/SB7x0 chipset */
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#define SP5100_SB_RESOURCE_MMIO_BASE 0x9C
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#define SP5100_PM_WATCHDOG_CONTROL 0x69
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#define SP5100_PM_WATCHDOG_BASE 0x6C
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#define SP5100_PCI_WATCHDOG_MISC_REG 0x41
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#define SP5100_PCI_WATCHDOG_DECODE_EN BIT(3)
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#define SP5100_PM_WATCHDOG_DISABLE ((u8)BIT(0))
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#define SP5100_PM_WATCHDOG_SECOND_RES GENMASK(2, 1)
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#define SP5100_DEVNAME "SP5100 TCO"
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/* For SB8x0(or later) chipset */
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#define SB800_PM_ACPI_MMIO_EN 0x24
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#define SB800_PM_WATCHDOG_CONTROL 0x48
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#define SB800_PM_WATCHDOG_BASE 0x48
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#define SB800_PM_WATCHDOG_CONFIG 0x4C
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#define SB800_PCI_WATCHDOG_DECODE_EN BIT(0)
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#define SB800_PM_WATCHDOG_DISABLE ((u8)BIT(1))
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#define SB800_PM_WATCHDOG_SECOND_RES GENMASK(1, 0)
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#define SB800_ACPI_MMIO_DECODE_EN BIT(0)
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#define SB800_ACPI_MMIO_SEL BIT(1)
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#define SB800_PM_WDT_MMIO_OFFSET 0xB00
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#define SB800_DEVNAME "SB800 TCO"
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/* For recent chips with embedded FCH (rev 40+) */
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#define EFCH_PM_DECODEEN 0x00
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#define EFCH_PM_DECODEEN_WDT_TMREN BIT(7)
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#define EFCH_PM_DECODEEN3 0x03
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#define EFCH_PM_DECODEEN_SECOND_RES GENMASK(1, 0)
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#define EFCH_PM_WATCHDOG_DISABLE ((u8)GENMASK(3, 2))
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/* WDT MMIO if enabled with PM00_DECODEEN_WDT_TMREN */
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#define EFCH_PM_WDT_ADDR 0xfeb00000
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#define EFCH_PM_ISACONTROL 0x04
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#define EFCH_PM_ISACONTROL_MMIOEN BIT(1)
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#define EFCH_PM_ACPI_MMIO_ADDR 0xfed80000
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#define EFCH_PM_ACPI_MMIO_WDT_OFFSET 0x00000b00
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