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39d7530d74
* support for chained PMU counters in guests * improved SError handling * handle Neoverse N1 erratum #1349291 * allow side-channel mitigation status to be migrated * standardise most AArch64 system register accesses to msr_s/mrs_s * fix host MPIDR corruption on 32bit * selftests ckleanups x86: * PMU event {white,black}listing * ability for the guest to disable host-side interrupt polling * fixes for enlightened VMCS (Hyper-V pv nested virtualization), * new hypercall to yield to IPI target * support for passing cstate MSRs through to the guest * lots of cleanups and optimizations Generic: * Some txt->rST conversions for the documentation -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQEcBAABAgAGBQJdJzdIAAoJEL/70l94x66DQDoH/i83/8kX4I8AWDlushPru4ts Q4lCE5VAPha+o4pLb1dtfFL3gTmSbsB1N++JSlqK3JOo6LphIOy6b0wBjQBbAa6U 3CT1dJaHJoScLLj09vyBlvClGUH2ZKEQTWOiquCCf7JfPofxwPUA6vJ7TYsdkckx zR3ygbADWmnfS7hFfiqN3JzuYh9eoooGNWSU+Giq6VF41SiL3IqhBGZhWS0zE9c2 2c5lpqqdeHmAYNBqsyzNiDRKp7+zLFSmZ7Z5/0L755L8KYwR6F5beTnmBMHvb4lA PWH/SWOC8EYR+PEowfrH+TxKZwp0gMn1kcAKjilHk0uCRwG1IzuHAr2jlNxICCk= =t/Oq -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm Pull KVM updates from Paolo Bonzini: "ARM: - support for chained PMU counters in guests - improved SError handling - handle Neoverse N1 erratum #1349291 - allow side-channel mitigation status to be migrated - standardise most AArch64 system register accesses to msr_s/mrs_s - fix host MPIDR corruption on 32bit - selftests ckleanups x86: - PMU event {white,black}listing - ability for the guest to disable host-side interrupt polling - fixes for enlightened VMCS (Hyper-V pv nested virtualization), - new hypercall to yield to IPI target - support for passing cstate MSRs through to the guest - lots of cleanups and optimizations Generic: - Some txt->rST conversions for the documentation" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (128 commits) Documentation: virtual: Add toctree hooks Documentation: kvm: Convert cpuid.txt to .rst Documentation: virtual: Convert paravirt_ops.txt to .rst KVM: x86: Unconditionally enable irqs in guest context KVM: x86: PMU Event Filter kvm: x86: Fix -Wmissing-prototypes warnings KVM: Properly check if "page" is valid in kvm_vcpu_unmap KVM: arm/arm64: Initialise host's MPIDRs by reading the actual register KVM: LAPIC: Retry tune per-vCPU timer_advance_ns if adaptive tuning goes insane kvm: LAPIC: write down valid APIC registers KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s KVM: doc: Add API documentation on the KVM_REG_ARM_WORKAROUNDS register KVM: arm/arm64: Add save/restore support for firmware workaround state arm64: KVM: Propagate full Spectre v2 workaround state to KVM guests KVM: arm/arm64: Support chained PMU counters KVM: arm/arm64: Remove pmc->bitmask KVM: arm/arm64: Re-create event when setting counter value KVM: arm/arm64: Extract duplicated code to own function KVM: arm/arm64: Rename kvm_pmu_{enable/disable}_counter functions KVM: LAPIC: ARBPRI is a reserved register for x2APIC ...
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=======================================
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Silicon Errata and Software Workarounds
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=======================================
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Author: Will Deacon <will.deacon@arm.com>
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Date : 27 November 2015
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It is an unfortunate fact of life that hardware is often produced with
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so-called "errata", which can cause it to deviate from the architecture
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under specific circumstances. For hardware produced by ARM, these
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errata are broadly classified into the following categories:
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========== ========================================================
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Category A A critical error without a viable workaround.
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Category B A significant or critical error with an acceptable
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workaround.
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Category C A minor error that is not expected to occur under normal
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operation.
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========== ========================================================
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For more information, consult one of the "Software Developers Errata
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Notice" documents available on infocenter.arm.com (registration
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required).
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As far as Linux is concerned, Category B errata may require some special
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treatment in the operating system. For example, avoiding a particular
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sequence of code, or configuring the processor in a particular way. A
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less common situation may require similar actions in order to declassify
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a Category A erratum into a Category C erratum. These are collectively
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known as "software workarounds" and are only required in the minority of
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cases (e.g. those cases that both require a non-secure workaround *and*
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can be triggered by Linux).
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For software workarounds that may adversely impact systems unaffected by
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the erratum in question, a Kconfig entry is added under "Kernel
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Features" -> "ARM errata workarounds via the alternatives framework".
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These are enabled by default and patched in at runtime when an affected
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CPU is detected. For less-intrusive workarounds, a Kconfig option is not
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available and the code is structured (preferably with a comment) in such
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a way that the erratum will not be hit.
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This approach can make it slightly onerous to determine exactly which
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errata are worked around in an arbitrary kernel source tree, so this
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file acts as a registry of software workarounds in the Linux Kernel and
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will be updated when new workarounds are committed and backported to
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stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| Implementor | Component | Erratum ID | Kconfig |
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+================+=================+=================+=============================+
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| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A57 | #852523 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A72 | #853709 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #1165522 | ARM64_ERRATUM_1165522 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #1286807 | ARM64_ERRATUM_1286807 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1349291 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | MMU-500 | #841119,826419 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX ITS | #22375,24313 | CAVIUM_ERRATUM_22375 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX Core | #30115 | CAVIUM_ERRATUM_30115 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX SMMUv2 | #27704 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX2 SMMUv3| #74 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX2 SMMUv3| #126 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Hisilicon | Hip0{6,7} | #161010701 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| Hisilicon | Hip07 | #161600802 | HISILICON_ERRATUM_161600802 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Hisilicon | Hip08 SMMU PMCG | #162001800 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Qualcomm Tech. | QDF2400 ITS | E0065 | QCOM_QDF2400_ERRATUM_0065 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Qualcomm Tech. | Falkor v{1,2} | E1041 | QCOM_FALKOR_ERRATUM_1041 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
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+----------------+-----------------+-----------------+-----------------------------+
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