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035b73b2b3
On Intel Tangier B0 and Anniedale the interrupt line, disregarding
to have different numbers, is shared between HSU DMA and UART IPs.
Thus on such SoCs we are expecting that IRQ handler is called in
UART driver only. hsu_pci_irq was handling the spurious interrupt
from HSU DMA by returning immediately. This wastes CPU time and
since HSU DMA and HSU UART interrupt occur simultaneously they race
to be handled causing delay to the HSU UART interrupt handling.
Fix this by disabling the interrupt entirely.
Fixes: 4831e0d905 ("serial: 8250_mid: handle interrupt correctly in DMA case")
Signed-off-by: Ferry Toth <ftoth@exalondelft.nl>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20210112223749.97036-1-ftoth@exalondelft.nl
Signed-off-by: Vinod Koul <vkoul@kernel.org>
144 lines
3.3 KiB
C
144 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* PCI driver for the High Speed UART DMA
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*
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* Copyright (C) 2015 Intel Corporation
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* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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*
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* Partially based on the bits found in drivers/tty/serial/mfd.c.
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*/
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include "hsu.h"
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#define HSU_PCI_DMASR 0x00
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#define HSU_PCI_DMAISR 0x04
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#define HSU_PCI_CHAN_OFFSET 0x100
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#define PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA 0x081e
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#define PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA 0x1192
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static irqreturn_t hsu_pci_irq(int irq, void *dev)
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{
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struct hsu_dma_chip *chip = dev;
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u32 dmaisr;
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u32 status;
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unsigned short i;
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int ret = 0;
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int err;
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dmaisr = readl(chip->regs + HSU_PCI_DMAISR);
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for (i = 0; i < chip->hsu->nr_channels; i++) {
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if (dmaisr & 0x1) {
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err = hsu_dma_get_status(chip, i, &status);
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if (err > 0)
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ret |= 1;
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else if (err == 0)
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ret |= hsu_dma_do_irq(chip, i, status);
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}
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dmaisr >>= 1;
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}
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return IRQ_RETVAL(ret);
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}
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static int hsu_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct hsu_dma_chip *chip;
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int ret;
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ret = pcim_enable_device(pdev);
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if (ret)
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return ret;
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ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
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if (ret) {
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dev_err(&pdev->dev, "I/O memory remapping failed\n");
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return ret;
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}
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pci_set_master(pdev);
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pci_try_set_mwi(pdev);
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ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (ret)
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return ret;
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ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
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if (ret)
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return ret;
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chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
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if (ret < 0)
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return ret;
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chip->dev = &pdev->dev;
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chip->regs = pcim_iomap_table(pdev)[0];
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chip->length = pci_resource_len(pdev, 0);
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chip->offset = HSU_PCI_CHAN_OFFSET;
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chip->irq = pci_irq_vector(pdev, 0);
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ret = hsu_dma_probe(chip);
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if (ret)
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return ret;
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ret = request_irq(chip->irq, hsu_pci_irq, 0, "hsu_dma_pci", chip);
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if (ret)
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goto err_register_irq;
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/*
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* On Intel Tangier B0 and Anniedale the interrupt line, disregarding
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* to have different numbers, is shared between HSU DMA and UART IPs.
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* Thus on such SoCs we are expecting that IRQ handler is called in
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* UART driver only. Instead of handling the spurious interrupt
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* from HSU DMA here and waste CPU time and delay HSU UART interrupt
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* handling, disable the interrupt entirely.
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*/
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if (pdev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA)
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disable_irq_nosync(chip->irq);
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pci_set_drvdata(pdev, chip);
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return 0;
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err_register_irq:
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hsu_dma_remove(chip);
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return ret;
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}
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static void hsu_pci_remove(struct pci_dev *pdev)
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{
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struct hsu_dma_chip *chip = pci_get_drvdata(pdev);
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free_irq(chip->irq, chip);
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hsu_dma_remove(chip);
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}
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static const struct pci_device_id hsu_pci_id_table[] = {
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA), 0 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA), 0 },
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{ }
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};
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MODULE_DEVICE_TABLE(pci, hsu_pci_id_table);
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static struct pci_driver hsu_pci_driver = {
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.name = "hsu_dma_pci",
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.id_table = hsu_pci_id_table,
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.probe = hsu_pci_probe,
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.remove = hsu_pci_remove,
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};
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module_pci_driver(hsu_pci_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("High Speed UART DMA PCI driver");
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MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
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