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![Dave Jiang](/assets/img/avatar_default.png)
Create a dedicated lock for device command operations. Put the device command operation under finer grained locking instead of using the idxd->dev_lock. Suggested-by: Sanjay Kumar <sanjay.k.kumar@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/161894525685.3210132.16160045731436382560.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
1088 lines
25 KiB
C
1088 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/dmaengine.h>
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include <uapi/linux/idxd.h>
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#include "../dmaengine.h"
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#include "idxd.h"
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#include "registers.h"
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static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
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u32 *status);
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/* Interrupt control bits */
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void idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id)
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{
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struct irq_data *data = irq_get_irq_data(idxd->irq_entries[vec_id].vector);
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pci_msi_mask_irq(data);
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}
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void idxd_mask_msix_vectors(struct idxd_device *idxd)
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{
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struct pci_dev *pdev = idxd->pdev;
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int msixcnt = pci_msix_vec_count(pdev);
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int i;
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for (i = 0; i < msixcnt; i++)
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idxd_mask_msix_vector(idxd, i);
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}
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void idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id)
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{
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struct irq_data *data = irq_get_irq_data(idxd->irq_entries[vec_id].vector);
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pci_msi_unmask_irq(data);
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}
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void idxd_unmask_error_interrupts(struct idxd_device *idxd)
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{
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union genctrl_reg genctrl;
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genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
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genctrl.softerr_int_en = 1;
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genctrl.halt_int_en = 1;
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iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
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}
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void idxd_mask_error_interrupts(struct idxd_device *idxd)
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{
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union genctrl_reg genctrl;
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genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
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genctrl.softerr_int_en = 0;
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genctrl.halt_int_en = 0;
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iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
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}
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static void free_hw_descs(struct idxd_wq *wq)
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{
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int i;
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for (i = 0; i < wq->num_descs; i++)
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kfree(wq->hw_descs[i]);
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kfree(wq->hw_descs);
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}
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static int alloc_hw_descs(struct idxd_wq *wq, int num)
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{
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struct device *dev = &wq->idxd->pdev->dev;
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int i;
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int node = dev_to_node(dev);
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wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *),
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GFP_KERNEL, node);
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if (!wq->hw_descs)
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return -ENOMEM;
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for (i = 0; i < num; i++) {
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wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]),
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GFP_KERNEL, node);
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if (!wq->hw_descs[i]) {
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free_hw_descs(wq);
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return -ENOMEM;
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}
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}
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return 0;
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}
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static void free_descs(struct idxd_wq *wq)
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{
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int i;
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for (i = 0; i < wq->num_descs; i++)
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kfree(wq->descs[i]);
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kfree(wq->descs);
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}
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static int alloc_descs(struct idxd_wq *wq, int num)
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{
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struct device *dev = &wq->idxd->pdev->dev;
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int i;
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int node = dev_to_node(dev);
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wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *),
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GFP_KERNEL, node);
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if (!wq->descs)
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return -ENOMEM;
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for (i = 0; i < num; i++) {
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wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]),
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GFP_KERNEL, node);
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if (!wq->descs[i]) {
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free_descs(wq);
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return -ENOMEM;
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}
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}
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return 0;
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}
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/* WQ control bits */
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int idxd_wq_alloc_resources(struct idxd_wq *wq)
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{
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struct idxd_device *idxd = wq->idxd;
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struct device *dev = &idxd->pdev->dev;
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int rc, num_descs, i;
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int align;
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u64 tmp;
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if (wq->type != IDXD_WQT_KERNEL)
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return 0;
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wq->num_descs = wq->size;
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num_descs = wq->size;
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rc = alloc_hw_descs(wq, num_descs);
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if (rc < 0)
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return rc;
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align = idxd->data->align;
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wq->compls_size = num_descs * idxd->data->compl_size + align;
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wq->compls_raw = dma_alloc_coherent(dev, wq->compls_size,
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&wq->compls_addr_raw, GFP_KERNEL);
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if (!wq->compls_raw) {
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rc = -ENOMEM;
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goto fail_alloc_compls;
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}
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/* Adjust alignment */
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wq->compls_addr = (wq->compls_addr_raw + (align - 1)) & ~(align - 1);
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tmp = (u64)wq->compls_raw;
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tmp = (tmp + (align - 1)) & ~(align - 1);
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wq->compls = (struct dsa_completion_record *)tmp;
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rc = alloc_descs(wq, num_descs);
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if (rc < 0)
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goto fail_alloc_descs;
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rc = sbitmap_queue_init_node(&wq->sbq, num_descs, -1, false, GFP_KERNEL,
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dev_to_node(dev));
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if (rc < 0)
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goto fail_sbitmap_init;
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for (i = 0; i < num_descs; i++) {
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struct idxd_desc *desc = wq->descs[i];
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desc->hw = wq->hw_descs[i];
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if (idxd->data->type == IDXD_TYPE_DSA)
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desc->completion = &wq->compls[i];
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else if (idxd->data->type == IDXD_TYPE_IAX)
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desc->iax_completion = &wq->iax_compls[i];
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desc->compl_dma = wq->compls_addr + idxd->data->compl_size * i;
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desc->id = i;
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desc->wq = wq;
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desc->cpu = -1;
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}
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return 0;
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fail_sbitmap_init:
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free_descs(wq);
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fail_alloc_descs:
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dma_free_coherent(dev, wq->compls_size, wq->compls_raw,
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wq->compls_addr_raw);
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fail_alloc_compls:
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free_hw_descs(wq);
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return rc;
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}
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void idxd_wq_free_resources(struct idxd_wq *wq)
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{
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struct device *dev = &wq->idxd->pdev->dev;
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if (wq->type != IDXD_WQT_KERNEL)
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return;
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free_hw_descs(wq);
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free_descs(wq);
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dma_free_coherent(dev, wq->compls_size, wq->compls_raw,
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wq->compls_addr_raw);
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sbitmap_queue_free(&wq->sbq);
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}
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int idxd_wq_enable(struct idxd_wq *wq)
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{
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struct idxd_device *idxd = wq->idxd;
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struct device *dev = &idxd->pdev->dev;
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u32 status;
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if (wq->state == IDXD_WQ_ENABLED) {
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dev_dbg(dev, "WQ %d already enabled\n", wq->id);
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return -ENXIO;
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}
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idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_WQ, wq->id, &status);
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if (status != IDXD_CMDSTS_SUCCESS &&
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status != IDXD_CMDSTS_ERR_WQ_ENABLED) {
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dev_dbg(dev, "WQ enable failed: %#x\n", status);
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return -ENXIO;
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}
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wq->state = IDXD_WQ_ENABLED;
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dev_dbg(dev, "WQ %d enabled\n", wq->id);
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return 0;
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}
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int idxd_wq_disable(struct idxd_wq *wq)
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{
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struct idxd_device *idxd = wq->idxd;
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struct device *dev = &idxd->pdev->dev;
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u32 status, operand;
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dev_dbg(dev, "Disabling WQ %d\n", wq->id);
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if (wq->state != IDXD_WQ_ENABLED) {
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dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
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return 0;
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}
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operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
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idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_WQ, operand, &status);
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if (status != IDXD_CMDSTS_SUCCESS) {
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dev_dbg(dev, "WQ disable failed: %#x\n", status);
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return -ENXIO;
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}
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wq->state = IDXD_WQ_DISABLED;
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dev_dbg(dev, "WQ %d disabled\n", wq->id);
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return 0;
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}
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void idxd_wq_drain(struct idxd_wq *wq)
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{
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struct idxd_device *idxd = wq->idxd;
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struct device *dev = &idxd->pdev->dev;
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u32 operand;
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if (wq->state != IDXD_WQ_ENABLED) {
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dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
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return;
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}
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dev_dbg(dev, "Draining WQ %d\n", wq->id);
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operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
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idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_WQ, operand, NULL);
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}
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void idxd_wq_reset(struct idxd_wq *wq)
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{
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struct idxd_device *idxd = wq->idxd;
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struct device *dev = &idxd->pdev->dev;
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u32 operand;
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if (wq->state != IDXD_WQ_ENABLED) {
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dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
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return;
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}
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operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
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idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, NULL);
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wq->state = IDXD_WQ_DISABLED;
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}
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int idxd_wq_map_portal(struct idxd_wq *wq)
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{
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struct idxd_device *idxd = wq->idxd;
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struct pci_dev *pdev = idxd->pdev;
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struct device *dev = &pdev->dev;
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resource_size_t start;
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start = pci_resource_start(pdev, IDXD_WQ_BAR);
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start += idxd_get_wq_portal_full_offset(wq->id, IDXD_PORTAL_LIMITED);
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wq->portal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE);
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if (!wq->portal)
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return -ENOMEM;
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return 0;
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}
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void idxd_wq_unmap_portal(struct idxd_wq *wq)
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{
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struct device *dev = &wq->idxd->pdev->dev;
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devm_iounmap(dev, wq->portal);
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wq->portal = NULL;
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}
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void idxd_wqs_unmap_portal(struct idxd_device *idxd)
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{
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int i;
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for (i = 0; i < idxd->max_wqs; i++) {
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struct idxd_wq *wq = idxd->wqs[i];
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if (wq->portal)
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idxd_wq_unmap_portal(wq);
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}
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}
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int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid)
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{
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struct idxd_device *idxd = wq->idxd;
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int rc;
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union wqcfg wqcfg;
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unsigned int offset;
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unsigned long flags;
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rc = idxd_wq_disable(wq);
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if (rc < 0)
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return rc;
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offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX);
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spin_lock_irqsave(&idxd->dev_lock, flags);
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wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
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wqcfg.pasid_en = 1;
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wqcfg.pasid = pasid;
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iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
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spin_unlock_irqrestore(&idxd->dev_lock, flags);
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rc = idxd_wq_enable(wq);
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if (rc < 0)
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return rc;
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return 0;
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}
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int idxd_wq_disable_pasid(struct idxd_wq *wq)
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{
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struct idxd_device *idxd = wq->idxd;
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int rc;
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union wqcfg wqcfg;
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unsigned int offset;
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unsigned long flags;
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rc = idxd_wq_disable(wq);
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if (rc < 0)
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return rc;
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offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX);
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spin_lock_irqsave(&idxd->dev_lock, flags);
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wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
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wqcfg.pasid_en = 0;
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wqcfg.pasid = 0;
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iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
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spin_unlock_irqrestore(&idxd->dev_lock, flags);
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rc = idxd_wq_enable(wq);
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if (rc < 0)
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return rc;
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return 0;
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}
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void idxd_wq_disable_cleanup(struct idxd_wq *wq)
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{
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struct idxd_device *idxd = wq->idxd;
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lockdep_assert_held(&idxd->dev_lock);
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memset(wq->wqcfg, 0, idxd->wqcfg_size);
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wq->type = IDXD_WQT_NONE;
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wq->size = 0;
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wq->group = NULL;
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wq->threshold = 0;
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wq->priority = 0;
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wq->ats_dis = 0;
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clear_bit(WQ_FLAG_DEDICATED, &wq->flags);
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memset(wq->name, 0, WQ_NAME_SIZE);
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}
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static void idxd_wq_ref_release(struct percpu_ref *ref)
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{
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struct idxd_wq *wq = container_of(ref, struct idxd_wq, wq_active);
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complete(&wq->wq_dead);
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}
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int idxd_wq_init_percpu_ref(struct idxd_wq *wq)
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{
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int rc;
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memset(&wq->wq_active, 0, sizeof(wq->wq_active));
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rc = percpu_ref_init(&wq->wq_active, idxd_wq_ref_release, 0, GFP_KERNEL);
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if (rc < 0)
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return rc;
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reinit_completion(&wq->wq_dead);
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return 0;
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}
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void idxd_wq_quiesce(struct idxd_wq *wq)
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{
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percpu_ref_kill(&wq->wq_active);
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wait_for_completion(&wq->wq_dead);
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percpu_ref_exit(&wq->wq_active);
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}
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/* Device control bits */
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static inline bool idxd_is_enabled(struct idxd_device *idxd)
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{
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union gensts_reg gensts;
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gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
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if (gensts.state == IDXD_DEVICE_STATE_ENABLED)
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return true;
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return false;
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}
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static inline bool idxd_device_is_halted(struct idxd_device *idxd)
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{
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union gensts_reg gensts;
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gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
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return (gensts.state == IDXD_DEVICE_STATE_HALT);
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}
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/*
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* This is function is only used for reset during probe and will
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* poll for completion. Once the device is setup with interrupts,
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* all commands will be done via interrupt completion.
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*/
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int idxd_device_init_reset(struct idxd_device *idxd)
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{
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struct device *dev = &idxd->pdev->dev;
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union idxd_command_reg cmd;
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unsigned long flags;
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if (idxd_device_is_halted(idxd)) {
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dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
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return -ENXIO;
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}
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memset(&cmd, 0, sizeof(cmd));
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cmd.cmd = IDXD_CMD_RESET_DEVICE;
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dev_dbg(dev, "%s: sending reset for init.\n", __func__);
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spin_lock_irqsave(&idxd->cmd_lock, flags);
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iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
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while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) &
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IDXD_CMDSTS_ACTIVE)
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cpu_relax();
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|
spin_unlock_irqrestore(&idxd->cmd_lock, flags);
|
|
return 0;
|
|
}
|
|
|
|
static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
|
|
u32 *status)
|
|
{
|
|
union idxd_command_reg cmd;
|
|
DECLARE_COMPLETION_ONSTACK(done);
|
|
unsigned long flags;
|
|
|
|
if (idxd_device_is_halted(idxd)) {
|
|
dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
|
|
if (status)
|
|
*status = IDXD_CMDSTS_HW_ERR;
|
|
return;
|
|
}
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
cmd.cmd = cmd_code;
|
|
cmd.operand = operand;
|
|
cmd.int_req = 1;
|
|
|
|
spin_lock_irqsave(&idxd->cmd_lock, flags);
|
|
wait_event_lock_irq(idxd->cmd_waitq,
|
|
!test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags),
|
|
idxd->cmd_lock);
|
|
|
|
dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n",
|
|
__func__, cmd_code, operand);
|
|
|
|
idxd->cmd_status = 0;
|
|
__set_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags);
|
|
idxd->cmd_done = &done;
|
|
iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
|
|
|
|
/*
|
|
* After command submitted, release lock and go to sleep until
|
|
* the command completes via interrupt.
|
|
*/
|
|
spin_unlock_irqrestore(&idxd->cmd_lock, flags);
|
|
wait_for_completion(&done);
|
|
spin_lock_irqsave(&idxd->cmd_lock, flags);
|
|
if (status) {
|
|
*status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
|
|
idxd->cmd_status = *status & GENMASK(7, 0);
|
|
}
|
|
|
|
__clear_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags);
|
|
/* Wake up other pending commands */
|
|
wake_up(&idxd->cmd_waitq);
|
|
spin_unlock_irqrestore(&idxd->cmd_lock, flags);
|
|
}
|
|
|
|
int idxd_device_enable(struct idxd_device *idxd)
|
|
{
|
|
struct device *dev = &idxd->pdev->dev;
|
|
u32 status;
|
|
|
|
if (idxd_is_enabled(idxd)) {
|
|
dev_dbg(dev, "Device already enabled\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_DEVICE, 0, &status);
|
|
|
|
/* If the command is successful or if the device was enabled */
|
|
if (status != IDXD_CMDSTS_SUCCESS &&
|
|
status != IDXD_CMDSTS_ERR_DEV_ENABLED) {
|
|
dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
|
|
return -ENXIO;
|
|
}
|
|
|
|
idxd->state = IDXD_DEV_ENABLED;
|
|
return 0;
|
|
}
|
|
|
|
void idxd_device_wqs_clear_state(struct idxd_device *idxd)
|
|
{
|
|
int i;
|
|
|
|
lockdep_assert_held(&idxd->dev_lock);
|
|
|
|
for (i = 0; i < idxd->max_wqs; i++) {
|
|
struct idxd_wq *wq = idxd->wqs[i];
|
|
|
|
if (wq->state == IDXD_WQ_ENABLED) {
|
|
idxd_wq_disable_cleanup(wq);
|
|
wq->state = IDXD_WQ_DISABLED;
|
|
}
|
|
}
|
|
}
|
|
|
|
int idxd_device_disable(struct idxd_device *idxd)
|
|
{
|
|
struct device *dev = &idxd->pdev->dev;
|
|
u32 status;
|
|
unsigned long flags;
|
|
|
|
if (!idxd_is_enabled(idxd)) {
|
|
dev_dbg(dev, "Device is not enabled\n");
|
|
return 0;
|
|
}
|
|
|
|
idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_DEVICE, 0, &status);
|
|
|
|
/* If the command is successful or if the device was disabled */
|
|
if (status != IDXD_CMDSTS_SUCCESS &&
|
|
!(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) {
|
|
dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
|
|
return -ENXIO;
|
|
}
|
|
|
|
spin_lock_irqsave(&idxd->dev_lock, flags);
|
|
idxd_device_wqs_clear_state(idxd);
|
|
idxd->state = IDXD_DEV_CONF_READY;
|
|
spin_unlock_irqrestore(&idxd->dev_lock, flags);
|
|
return 0;
|
|
}
|
|
|
|
void idxd_device_reset(struct idxd_device *idxd)
|
|
{
|
|
unsigned long flags;
|
|
|
|
idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL);
|
|
spin_lock_irqsave(&idxd->dev_lock, flags);
|
|
idxd_device_wqs_clear_state(idxd);
|
|
idxd->state = IDXD_DEV_CONF_READY;
|
|
spin_unlock_irqrestore(&idxd->dev_lock, flags);
|
|
}
|
|
|
|
void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid)
|
|
{
|
|
struct device *dev = &idxd->pdev->dev;
|
|
u32 operand;
|
|
|
|
operand = pasid;
|
|
dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_DRAIN_PASID, operand);
|
|
idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_PASID, operand, NULL);
|
|
dev_dbg(dev, "pasid %d drained\n", pasid);
|
|
}
|
|
|
|
int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle,
|
|
enum idxd_interrupt_type irq_type)
|
|
{
|
|
struct device *dev = &idxd->pdev->dev;
|
|
u32 operand, status;
|
|
|
|
if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)))
|
|
return -EOPNOTSUPP;
|
|
|
|
dev_dbg(dev, "get int handle, idx %d\n", idx);
|
|
|
|
operand = idx & GENMASK(15, 0);
|
|
if (irq_type == IDXD_IRQ_IMS)
|
|
operand |= CMD_INT_HANDLE_IMS;
|
|
|
|
dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_REQUEST_INT_HANDLE, operand);
|
|
|
|
idxd_cmd_exec(idxd, IDXD_CMD_REQUEST_INT_HANDLE, operand, &status);
|
|
|
|
if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) {
|
|
dev_dbg(dev, "request int handle failed: %#x\n", status);
|
|
return -ENXIO;
|
|
}
|
|
|
|
*handle = (status >> IDXD_CMDSTS_RES_SHIFT) & GENMASK(15, 0);
|
|
|
|
dev_dbg(dev, "int handle acquired: %u\n", *handle);
|
|
return 0;
|
|
}
|
|
|
|
int idxd_device_release_int_handle(struct idxd_device *idxd, int handle,
|
|
enum idxd_interrupt_type irq_type)
|
|
{
|
|
struct device *dev = &idxd->pdev->dev;
|
|
u32 operand, status;
|
|
union idxd_command_reg cmd;
|
|
unsigned long flags;
|
|
|
|
if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE)))
|
|
return -EOPNOTSUPP;
|
|
|
|
dev_dbg(dev, "release int handle, handle %d\n", handle);
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
operand = handle & GENMASK(15, 0);
|
|
|
|
if (irq_type == IDXD_IRQ_IMS)
|
|
operand |= CMD_INT_HANDLE_IMS;
|
|
|
|
cmd.cmd = IDXD_CMD_RELEASE_INT_HANDLE;
|
|
cmd.operand = operand;
|
|
|
|
dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_RELEASE_INT_HANDLE, operand);
|
|
|
|
spin_lock_irqsave(&idxd->cmd_lock, flags);
|
|
iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
|
|
|
|
while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & IDXD_CMDSTS_ACTIVE)
|
|
cpu_relax();
|
|
status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
|
|
spin_unlock_irqrestore(&idxd->cmd_lock, flags);
|
|
|
|
if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) {
|
|
dev_dbg(dev, "release int handle failed: %#x\n", status);
|
|
return -ENXIO;
|
|
}
|
|
|
|
dev_dbg(dev, "int handle released.\n");
|
|
return 0;
|
|
}
|
|
|
|
/* Device configuration bits */
|
|
void idxd_msix_perm_setup(struct idxd_device *idxd)
|
|
{
|
|
union msix_perm mperm;
|
|
int i, msixcnt;
|
|
|
|
msixcnt = pci_msix_vec_count(idxd->pdev);
|
|
if (msixcnt < 0)
|
|
return;
|
|
|
|
mperm.bits = 0;
|
|
mperm.pasid = idxd->pasid;
|
|
mperm.pasid_en = device_pasid_enabled(idxd);
|
|
for (i = 1; i < msixcnt; i++)
|
|
iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + i * 8);
|
|
}
|
|
|
|
void idxd_msix_perm_clear(struct idxd_device *idxd)
|
|
{
|
|
union msix_perm mperm;
|
|
int i, msixcnt;
|
|
|
|
msixcnt = pci_msix_vec_count(idxd->pdev);
|
|
if (msixcnt < 0)
|
|
return;
|
|
|
|
mperm.bits = 0;
|
|
for (i = 1; i < msixcnt; i++)
|
|
iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + i * 8);
|
|
}
|
|
|
|
static void idxd_group_config_write(struct idxd_group *group)
|
|
{
|
|
struct idxd_device *idxd = group->idxd;
|
|
struct device *dev = &idxd->pdev->dev;
|
|
int i;
|
|
u32 grpcfg_offset;
|
|
|
|
dev_dbg(dev, "Writing group %d cfg registers\n", group->id);
|
|
|
|
/* setup GRPWQCFG */
|
|
for (i = 0; i < GRPWQCFG_STRIDES; i++) {
|
|
grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i);
|
|
iowrite64(group->grpcfg.wqs[i], idxd->reg_base + grpcfg_offset);
|
|
dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n",
|
|
group->id, i, grpcfg_offset,
|
|
ioread64(idxd->reg_base + grpcfg_offset));
|
|
}
|
|
|
|
/* setup GRPENGCFG */
|
|
grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id);
|
|
iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset);
|
|
dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id,
|
|
grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset));
|
|
|
|
/* setup GRPFLAGS */
|
|
grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id);
|
|
iowrite32(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset);
|
|
dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n",
|
|
group->id, grpcfg_offset,
|
|
ioread32(idxd->reg_base + grpcfg_offset));
|
|
}
|
|
|
|
static int idxd_groups_config_write(struct idxd_device *idxd)
|
|
|
|
{
|
|
union gencfg_reg reg;
|
|
int i;
|
|
struct device *dev = &idxd->pdev->dev;
|
|
|
|
/* Setup bandwidth token limit */
|
|
if (idxd->token_limit) {
|
|
reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
|
|
reg.token_limit = idxd->token_limit;
|
|
iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
|
|
}
|
|
|
|
dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET,
|
|
ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET));
|
|
|
|
for (i = 0; i < idxd->max_groups; i++) {
|
|
struct idxd_group *group = idxd->groups[i];
|
|
|
|
idxd_group_config_write(group);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idxd_wq_config_write(struct idxd_wq *wq)
|
|
{
|
|
struct idxd_device *idxd = wq->idxd;
|
|
struct device *dev = &idxd->pdev->dev;
|
|
u32 wq_offset;
|
|
int i;
|
|
|
|
if (!wq->group)
|
|
return 0;
|
|
|
|
/*
|
|
* Instead of memset the entire shadow copy of WQCFG, copy from the hardware after
|
|
* wq reset. This will copy back the sticky values that are present on some devices.
|
|
*/
|
|
for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
|
|
wq_offset = WQCFG_OFFSET(idxd, wq->id, i);
|
|
wq->wqcfg->bits[i] = ioread32(idxd->reg_base + wq_offset);
|
|
}
|
|
|
|
/* byte 0-3 */
|
|
wq->wqcfg->wq_size = wq->size;
|
|
|
|
if (wq->size == 0) {
|
|
dev_warn(dev, "Incorrect work queue size: 0\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* bytes 4-7 */
|
|
wq->wqcfg->wq_thresh = wq->threshold;
|
|
|
|
/* byte 8-11 */
|
|
wq->wqcfg->priv = !!(wq->type == IDXD_WQT_KERNEL);
|
|
if (wq_dedicated(wq))
|
|
wq->wqcfg->mode = 1;
|
|
|
|
if (device_pasid_enabled(idxd)) {
|
|
wq->wqcfg->pasid_en = 1;
|
|
if (wq->type == IDXD_WQT_KERNEL && wq_dedicated(wq))
|
|
wq->wqcfg->pasid = idxd->pasid;
|
|
}
|
|
|
|
wq->wqcfg->priority = wq->priority;
|
|
|
|
if (idxd->hw.gen_cap.block_on_fault &&
|
|
test_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags))
|
|
wq->wqcfg->bof = 1;
|
|
|
|
if (idxd->hw.wq_cap.wq_ats_support)
|
|
wq->wqcfg->wq_ats_disable = wq->ats_dis;
|
|
|
|
/* bytes 12-15 */
|
|
wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes);
|
|
wq->wqcfg->max_batch_shift = ilog2(wq->max_batch_size);
|
|
|
|
dev_dbg(dev, "WQ %d CFGs\n", wq->id);
|
|
for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
|
|
wq_offset = WQCFG_OFFSET(idxd, wq->id, i);
|
|
iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset);
|
|
dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n",
|
|
wq->id, i, wq_offset,
|
|
ioread32(idxd->reg_base + wq_offset));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idxd_wqs_config_write(struct idxd_device *idxd)
|
|
{
|
|
int i, rc;
|
|
|
|
for (i = 0; i < idxd->max_wqs; i++) {
|
|
struct idxd_wq *wq = idxd->wqs[i];
|
|
|
|
rc = idxd_wq_config_write(wq);
|
|
if (rc < 0)
|
|
return rc;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void idxd_group_flags_setup(struct idxd_device *idxd)
|
|
{
|
|
int i;
|
|
|
|
/* TC-A 0 and TC-B 1 should be defaults */
|
|
for (i = 0; i < idxd->max_groups; i++) {
|
|
struct idxd_group *group = idxd->groups[i];
|
|
|
|
if (group->tc_a == -1)
|
|
group->tc_a = group->grpcfg.flags.tc_a = 0;
|
|
else
|
|
group->grpcfg.flags.tc_a = group->tc_a;
|
|
if (group->tc_b == -1)
|
|
group->tc_b = group->grpcfg.flags.tc_b = 1;
|
|
else
|
|
group->grpcfg.flags.tc_b = group->tc_b;
|
|
group->grpcfg.flags.use_token_limit = group->use_token_limit;
|
|
group->grpcfg.flags.tokens_reserved = group->tokens_reserved;
|
|
if (group->tokens_allowed)
|
|
group->grpcfg.flags.tokens_allowed =
|
|
group->tokens_allowed;
|
|
else
|
|
group->grpcfg.flags.tokens_allowed = idxd->max_tokens;
|
|
}
|
|
}
|
|
|
|
static int idxd_engines_setup(struct idxd_device *idxd)
|
|
{
|
|
int i, engines = 0;
|
|
struct idxd_engine *eng;
|
|
struct idxd_group *group;
|
|
|
|
for (i = 0; i < idxd->max_groups; i++) {
|
|
group = idxd->groups[i];
|
|
group->grpcfg.engines = 0;
|
|
}
|
|
|
|
for (i = 0; i < idxd->max_engines; i++) {
|
|
eng = idxd->engines[i];
|
|
group = eng->group;
|
|
|
|
if (!group)
|
|
continue;
|
|
|
|
group->grpcfg.engines |= BIT(eng->id);
|
|
engines++;
|
|
}
|
|
|
|
if (!engines)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idxd_wqs_setup(struct idxd_device *idxd)
|
|
{
|
|
struct idxd_wq *wq;
|
|
struct idxd_group *group;
|
|
int i, j, configured = 0;
|
|
struct device *dev = &idxd->pdev->dev;
|
|
|
|
for (i = 0; i < idxd->max_groups; i++) {
|
|
group = idxd->groups[i];
|
|
for (j = 0; j < 4; j++)
|
|
group->grpcfg.wqs[j] = 0;
|
|
}
|
|
|
|
for (i = 0; i < idxd->max_wqs; i++) {
|
|
wq = idxd->wqs[i];
|
|
group = wq->group;
|
|
|
|
if (!wq->group)
|
|
continue;
|
|
if (!wq->size)
|
|
continue;
|
|
|
|
if (wq_shared(wq) && !device_swq_supported(idxd)) {
|
|
dev_warn(dev, "No shared wq support but configured.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64);
|
|
configured++;
|
|
}
|
|
|
|
if (configured == 0)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int idxd_device_config(struct idxd_device *idxd)
|
|
{
|
|
int rc;
|
|
|
|
lockdep_assert_held(&idxd->dev_lock);
|
|
rc = idxd_wqs_setup(idxd);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
rc = idxd_engines_setup(idxd);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
idxd_group_flags_setup(idxd);
|
|
|
|
rc = idxd_wqs_config_write(idxd);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
rc = idxd_groups_config_write(idxd);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idxd_wq_load_config(struct idxd_wq *wq)
|
|
{
|
|
struct idxd_device *idxd = wq->idxd;
|
|
struct device *dev = &idxd->pdev->dev;
|
|
int wqcfg_offset;
|
|
int i;
|
|
|
|
wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, 0);
|
|
memcpy_fromio(wq->wqcfg, idxd->reg_base + wqcfg_offset, idxd->wqcfg_size);
|
|
|
|
wq->size = wq->wqcfg->wq_size;
|
|
wq->threshold = wq->wqcfg->wq_thresh;
|
|
if (wq->wqcfg->priv)
|
|
wq->type = IDXD_WQT_KERNEL;
|
|
|
|
/* The driver does not support shared WQ mode in read-only config yet */
|
|
if (wq->wqcfg->mode == 0 || wq->wqcfg->pasid_en)
|
|
return -EOPNOTSUPP;
|
|
|
|
set_bit(WQ_FLAG_DEDICATED, &wq->flags);
|
|
|
|
wq->priority = wq->wqcfg->priority;
|
|
|
|
for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
|
|
wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i);
|
|
dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", wq->id, i, wqcfg_offset, wq->wqcfg->bits[i]);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void idxd_group_load_config(struct idxd_group *group)
|
|
{
|
|
struct idxd_device *idxd = group->idxd;
|
|
struct device *dev = &idxd->pdev->dev;
|
|
int i, j, grpcfg_offset;
|
|
|
|
/*
|
|
* Load WQS bit fields
|
|
* Iterate through all 256 bits 64 bits at a time
|
|
*/
|
|
for (i = 0; i < GRPWQCFG_STRIDES; i++) {
|
|
struct idxd_wq *wq;
|
|
|
|
grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i);
|
|
group->grpcfg.wqs[i] = ioread64(idxd->reg_base + grpcfg_offset);
|
|
dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n",
|
|
group->id, i, grpcfg_offset, group->grpcfg.wqs[i]);
|
|
|
|
if (i * 64 >= idxd->max_wqs)
|
|
break;
|
|
|
|
/* Iterate through all 64 bits and check for wq set */
|
|
for (j = 0; j < 64; j++) {
|
|
int id = i * 64 + j;
|
|
|
|
/* No need to check beyond max wqs */
|
|
if (id >= idxd->max_wqs)
|
|
break;
|
|
|
|
/* Set group assignment for wq if wq bit is set */
|
|
if (group->grpcfg.wqs[i] & BIT(j)) {
|
|
wq = idxd->wqs[id];
|
|
wq->group = group;
|
|
}
|
|
}
|
|
}
|
|
|
|
grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id);
|
|
group->grpcfg.engines = ioread64(idxd->reg_base + grpcfg_offset);
|
|
dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id,
|
|
grpcfg_offset, group->grpcfg.engines);
|
|
|
|
/* Iterate through all 64 bits to check engines set */
|
|
for (i = 0; i < 64; i++) {
|
|
if (i >= idxd->max_engines)
|
|
break;
|
|
|
|
if (group->grpcfg.engines & BIT(i)) {
|
|
struct idxd_engine *engine = idxd->engines[i];
|
|
|
|
engine->group = group;
|
|
}
|
|
}
|
|
|
|
grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id);
|
|
group->grpcfg.flags.bits = ioread32(idxd->reg_base + grpcfg_offset);
|
|
dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n",
|
|
group->id, grpcfg_offset, group->grpcfg.flags.bits);
|
|
}
|
|
|
|
int idxd_device_load_config(struct idxd_device *idxd)
|
|
{
|
|
union gencfg_reg reg;
|
|
int i, rc;
|
|
|
|
reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
|
|
idxd->token_limit = reg.token_limit;
|
|
|
|
for (i = 0; i < idxd->max_groups; i++) {
|
|
struct idxd_group *group = idxd->groups[i];
|
|
|
|
idxd_group_load_config(group);
|
|
}
|
|
|
|
for (i = 0; i < idxd->max_wqs; i++) {
|
|
struct idxd_wq *wq = idxd->wqs[i];
|
|
|
|
rc = idxd_wq_load_config(wq);
|
|
if (rc < 0)
|
|
return rc;
|
|
}
|
|
|
|
return 0;
|
|
}
|