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![Tom Zanussi](/assets/img/avatar_default.png)
Add the code needed in the main IDXD driver to interface with the IDXD perfmon implementation. [ Based on work originally by Jing Lin. ] Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com> Link: https://lore.kernel.org/r/a5564a5583911565d31c2af9234218c5166c4b2c.1619276133.git.zanussi@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
388 lines
9.5 KiB
C
388 lines
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/dmaengine.h>
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#include <uapi/linux/idxd.h>
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#include "../dmaengine.h"
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#include "idxd.h"
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#include "registers.h"
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enum irq_work_type {
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IRQ_WORK_NORMAL = 0,
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IRQ_WORK_PROCESS_FAULT,
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};
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struct idxd_fault {
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struct work_struct work;
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u64 addr;
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struct idxd_device *idxd;
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};
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static int irq_process_work_list(struct idxd_irq_entry *irq_entry,
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enum irq_work_type wtype,
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int *processed, u64 data);
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static int irq_process_pending_llist(struct idxd_irq_entry *irq_entry,
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enum irq_work_type wtype,
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int *processed, u64 data);
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static void idxd_device_reinit(struct work_struct *work)
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{
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struct idxd_device *idxd = container_of(work, struct idxd_device, work);
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struct device *dev = &idxd->pdev->dev;
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int rc, i;
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idxd_device_reset(idxd);
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rc = idxd_device_config(idxd);
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if (rc < 0)
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goto out;
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rc = idxd_device_enable(idxd);
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if (rc < 0)
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goto out;
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for (i = 0; i < idxd->max_wqs; i++) {
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struct idxd_wq *wq = idxd->wqs[i];
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if (wq->state == IDXD_WQ_ENABLED) {
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rc = idxd_wq_enable(wq);
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if (rc < 0) {
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dev_warn(dev, "Unable to re-enable wq %s\n",
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dev_name(&wq->conf_dev));
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}
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}
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}
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return;
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out:
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idxd_device_wqs_clear_state(idxd);
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}
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static void idxd_device_fault_work(struct work_struct *work)
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{
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struct idxd_fault *fault = container_of(work, struct idxd_fault, work);
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struct idxd_irq_entry *ie;
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int i;
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int processed;
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int irqcnt = fault->idxd->num_wq_irqs + 1;
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for (i = 1; i < irqcnt; i++) {
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ie = &fault->idxd->irq_entries[i];
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irq_process_work_list(ie, IRQ_WORK_PROCESS_FAULT,
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&processed, fault->addr);
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if (processed)
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break;
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irq_process_pending_llist(ie, IRQ_WORK_PROCESS_FAULT,
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&processed, fault->addr);
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if (processed)
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break;
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}
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kfree(fault);
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}
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static int idxd_device_schedule_fault_process(struct idxd_device *idxd,
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u64 fault_addr)
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{
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struct idxd_fault *fault;
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fault = kmalloc(sizeof(*fault), GFP_ATOMIC);
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if (!fault)
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return -ENOMEM;
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fault->addr = fault_addr;
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fault->idxd = idxd;
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INIT_WORK(&fault->work, idxd_device_fault_work);
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queue_work(idxd->wq, &fault->work);
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return 0;
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}
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static int process_misc_interrupts(struct idxd_device *idxd, u32 cause)
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{
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struct device *dev = &idxd->pdev->dev;
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union gensts_reg gensts;
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u32 val = 0;
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int i;
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bool err = false;
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if (cause & IDXD_INTC_ERR) {
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spin_lock_bh(&idxd->dev_lock);
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for (i = 0; i < 4; i++)
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idxd->sw_err.bits[i] = ioread64(idxd->reg_base +
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IDXD_SWERR_OFFSET + i * sizeof(u64));
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iowrite64(idxd->sw_err.bits[0] & IDXD_SWERR_ACK,
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idxd->reg_base + IDXD_SWERR_OFFSET);
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if (idxd->sw_err.valid && idxd->sw_err.wq_idx_valid) {
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int id = idxd->sw_err.wq_idx;
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struct idxd_wq *wq = idxd->wqs[id];
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if (wq->type == IDXD_WQT_USER)
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wake_up_interruptible(&wq->err_queue);
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} else {
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int i;
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for (i = 0; i < idxd->max_wqs; i++) {
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struct idxd_wq *wq = idxd->wqs[i];
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if (wq->type == IDXD_WQT_USER)
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wake_up_interruptible(&wq->err_queue);
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}
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}
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spin_unlock_bh(&idxd->dev_lock);
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val |= IDXD_INTC_ERR;
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for (i = 0; i < 4; i++)
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dev_warn(dev, "err[%d]: %#16.16llx\n",
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i, idxd->sw_err.bits[i]);
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err = true;
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}
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if (cause & IDXD_INTC_CMD) {
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val |= IDXD_INTC_CMD;
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complete(idxd->cmd_done);
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}
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if (cause & IDXD_INTC_OCCUPY) {
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/* Driver does not utilize occupancy interrupt */
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val |= IDXD_INTC_OCCUPY;
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}
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if (cause & IDXD_INTC_PERFMON_OVFL) {
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val |= IDXD_INTC_PERFMON_OVFL;
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perfmon_counter_overflow(idxd);
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}
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val ^= cause;
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if (val)
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dev_warn_once(dev, "Unexpected interrupt cause bits set: %#x\n",
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val);
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if (!err)
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return 0;
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/*
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* This case should rarely happen and typically is due to software
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* programming error by the driver.
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*/
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if (idxd->sw_err.valid &&
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idxd->sw_err.desc_valid &&
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idxd->sw_err.fault_addr)
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idxd_device_schedule_fault_process(idxd, idxd->sw_err.fault_addr);
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gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
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if (gensts.state == IDXD_DEVICE_STATE_HALT) {
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idxd->state = IDXD_DEV_HALTED;
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if (gensts.reset_type == IDXD_DEVICE_RESET_SOFTWARE) {
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/*
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* If we need a software reset, we will throw the work
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* on a system workqueue in order to allow interrupts
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* for the device command completions.
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*/
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INIT_WORK(&idxd->work, idxd_device_reinit);
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queue_work(idxd->wq, &idxd->work);
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} else {
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spin_lock_bh(&idxd->dev_lock);
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idxd_wqs_quiesce(idxd);
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idxd_wqs_unmap_portal(idxd);
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idxd_device_wqs_clear_state(idxd);
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dev_err(&idxd->pdev->dev,
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"idxd halted, need %s.\n",
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gensts.reset_type == IDXD_DEVICE_RESET_FLR ?
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"FLR" : "system reset");
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spin_unlock_bh(&idxd->dev_lock);
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return -ENXIO;
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}
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}
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return 0;
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}
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irqreturn_t idxd_misc_thread(int vec, void *data)
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{
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struct idxd_irq_entry *irq_entry = data;
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struct idxd_device *idxd = irq_entry->idxd;
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int rc;
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u32 cause;
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cause = ioread32(idxd->reg_base + IDXD_INTCAUSE_OFFSET);
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if (cause)
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iowrite32(cause, idxd->reg_base + IDXD_INTCAUSE_OFFSET);
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while (cause) {
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rc = process_misc_interrupts(idxd, cause);
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if (rc < 0)
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break;
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cause = ioread32(idxd->reg_base + IDXD_INTCAUSE_OFFSET);
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if (cause)
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iowrite32(cause, idxd->reg_base + IDXD_INTCAUSE_OFFSET);
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}
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return IRQ_HANDLED;
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}
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static inline bool match_fault(struct idxd_desc *desc, u64 fault_addr)
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{
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/*
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* Completion address can be bad as well. Check fault address match for descriptor
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* and completion address.
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*/
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if ((u64)desc->hw == fault_addr || (u64)desc->completion == fault_addr) {
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struct idxd_device *idxd = desc->wq->idxd;
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struct device *dev = &idxd->pdev->dev;
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dev_warn(dev, "desc with fault address: %#llx\n", fault_addr);
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return true;
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}
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return false;
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}
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static inline void complete_desc(struct idxd_desc *desc, enum idxd_complete_type reason)
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{
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idxd_dma_complete_txd(desc, reason);
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idxd_free_desc(desc->wq, desc);
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}
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static int irq_process_pending_llist(struct idxd_irq_entry *irq_entry,
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enum irq_work_type wtype,
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int *processed, u64 data)
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{
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struct idxd_desc *desc, *t;
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struct llist_node *head;
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int queued = 0;
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unsigned long flags;
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enum idxd_complete_type reason;
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*processed = 0;
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head = llist_del_all(&irq_entry->pending_llist);
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if (!head)
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goto out;
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if (wtype == IRQ_WORK_NORMAL)
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reason = IDXD_COMPLETE_NORMAL;
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else
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reason = IDXD_COMPLETE_DEV_FAIL;
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llist_for_each_entry_safe(desc, t, head, llnode) {
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if (desc->completion->status) {
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if ((desc->completion->status & DSA_COMP_STATUS_MASK) != DSA_COMP_SUCCESS)
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match_fault(desc, data);
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complete_desc(desc, reason);
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(*processed)++;
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} else {
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spin_lock_irqsave(&irq_entry->list_lock, flags);
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list_add_tail(&desc->list,
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&irq_entry->work_list);
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spin_unlock_irqrestore(&irq_entry->list_lock, flags);
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queued++;
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}
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}
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out:
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return queued;
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}
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static int irq_process_work_list(struct idxd_irq_entry *irq_entry,
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enum irq_work_type wtype,
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int *processed, u64 data)
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{
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int queued = 0;
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unsigned long flags;
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LIST_HEAD(flist);
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struct idxd_desc *desc, *n;
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enum idxd_complete_type reason;
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*processed = 0;
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if (wtype == IRQ_WORK_NORMAL)
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reason = IDXD_COMPLETE_NORMAL;
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else
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reason = IDXD_COMPLETE_DEV_FAIL;
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/*
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* This lock protects list corruption from access of list outside of the irq handler
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* thread.
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*/
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spin_lock_irqsave(&irq_entry->list_lock, flags);
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if (list_empty(&irq_entry->work_list)) {
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spin_unlock_irqrestore(&irq_entry->list_lock, flags);
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return 0;
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}
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list_for_each_entry_safe(desc, n, &irq_entry->work_list, list) {
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if (desc->completion->status) {
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list_del(&desc->list);
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(*processed)++;
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list_add_tail(&desc->list, &flist);
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} else {
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queued++;
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}
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}
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spin_unlock_irqrestore(&irq_entry->list_lock, flags);
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list_for_each_entry(desc, &flist, list) {
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if ((desc->completion->status & DSA_COMP_STATUS_MASK) != DSA_COMP_SUCCESS)
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match_fault(desc, data);
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complete_desc(desc, reason);
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}
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return queued;
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}
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static int idxd_desc_process(struct idxd_irq_entry *irq_entry)
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{
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int rc, processed, total = 0;
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/*
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* There are two lists we are processing. The pending_llist is where
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* submmiter adds all the submitted descriptor after sending it to
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* the workqueue. It's a lockless singly linked list. The work_list
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* is the common linux double linked list. We are in a scenario of
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* multiple producers and a single consumer. The producers are all
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* the kernel submitters of descriptors, and the consumer is the
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* kernel irq handler thread for the msix vector when using threaded
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* irq. To work with the restrictions of llist to remain lockless,
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* we are doing the following steps:
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* 1. Iterate through the work_list and process any completed
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* descriptor. Delete the completed entries during iteration.
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* 2. llist_del_all() from the pending list.
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* 3. Iterate through the llist that was deleted from the pending list
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* and process the completed entries.
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* 4. If the entry is still waiting on hardware, list_add_tail() to
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* the work_list.
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* 5. Repeat until no more descriptors.
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*/
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do {
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rc = irq_process_work_list(irq_entry, IRQ_WORK_NORMAL,
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&processed, 0);
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total += processed;
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if (rc != 0)
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continue;
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rc = irq_process_pending_llist(irq_entry, IRQ_WORK_NORMAL,
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&processed, 0);
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total += processed;
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} while (rc != 0);
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return total;
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}
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irqreturn_t idxd_wq_thread(int irq, void *data)
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{
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struct idxd_irq_entry *irq_entry = data;
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int processed;
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processed = idxd_desc_process(irq_entry);
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if (processed == 0)
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return IRQ_NONE;
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return IRQ_HANDLED;
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}
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