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- Add support in dmaengine core to do device node checks for DT devices and update bunch of drivers to use that and remove open coding from drivers - New driver/driver support for new hardware, namely: - MediaTek UART APDMA - Freescale i.mx7ulp edma2 - Synopsys eDMA IP core version 0 - Allwinner H6 DMA - Updates to axi-dma and support for interleaved cyclic transfers - Greg's debugfs return value check removals on drivers - Updates to stm32-dma, hsu, dw, pl330, tegra drivers -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJdLKxYAAoJEHwUBw8lI4NHsH8P/AqYZpUlLthe5L4qItzM1Uf0 HqxsJYs0xworjSRml8uptx/TzjIgJnJfEk2PV5VA+0zJNz/HnH7lDH85wKDx1Ydl AatUuyAFRO3GZOup/hY0AEIPhoIMdg/3zS2aapjJmaEZCVK2eVKmcj0KMvO5g0cw tsmXm3O0xd2Na1ToslNyYgFfCn8ortuAeoKiXJxhivMbGjRfw4LW/RPgS17Vspvh mEuxNXFWAZ+DorgPF5BmDPZ+LXcGgCXGNIoj64W+VHaXU5yXnlky+6/0f7cEcFEd yl3hjXVwyAq5zIItIOmiuozZidi5yfoizXg4S2ZD3P4xXKZ5OZ9Gf/0SMyXUIErU pwGxo6ZgsBcEpAHtqySELQedttttID+jYYeWU6oDr2LOy3W3F7AHOEGg9l9ZllLh gRdIoz3PrMK1wy/9Ytl37xklZyBk+HJLkeoIAvjrNgNJ1YRKqcysUCwsmqO7SG3N HnIGx74sG8ChljT/yX5pElq3ip6qLdb4pJcsfxKJ9VSxsTZ3JNINGNQtvI19hKR/ 6sn/c1Rb5/S1WxINGr+2FxChxXF8OESCN6GIEu6mNYVBzQnNPzwgPxfAGCqdoOOH mqXXgYNePMaBGYXBkdgvP1CnqenRRmTYo/1L4QmI4Mve4xpd5zhx5cZt9FlQJ2Im /hVT8gZ6bIrutsVOy4rg =R+aC -----END PGP SIGNATURE----- Merge tag 'dmaengine-5.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma Pull dmaengine updates from Vinod Koul: - Add support in dmaengine core to do device node checks for DT devices and update bunch of drivers to use that and remove open coding from drivers - New driver/driver support for new hardware, namely: - MediaTek UART APDMA - Freescale i.mx7ulp edma2 - Synopsys eDMA IP core version 0 - Allwinner H6 DMA - Updates to axi-dma and support for interleaved cyclic transfers - Greg's debugfs return value check removals on drivers - Updates to stm32-dma, hsu, dw, pl330, tegra drivers * tag 'dmaengine-5.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (68 commits) dmaengine: Revert "dmaengine: fsl-edma: add i.mx7ulp edma2 version support" dmaengine: at_xdmac: check for non-empty xfers_list before invoking callback Documentation: dmaengine: clean up description of dmatest usage dmaengine: tegra210-adma: remove PM_CLK dependency dmaengine: fsl-edma: add i.mx7ulp edma2 version support dt-bindings: dma: fsl-edma: add new i.mx7ulp-edma dmaengine: fsl-edma-common: version check for v2 instead dmaengine: fsl-edma-common: move dmamux register to another single function dmaengine: fsl-edma: add drvdata for fsl-edma dmaengine: Revert "dmaengine: fsl-edma: support little endian for edma driver" dmaengine: rcar-dmac: Reject zero-length slave DMA requests dmaengine: dw: Enable iDMA 32-bit on Intel Elkhart Lake dmaengine: dw-edma: fix semicolon.cocci warnings dmaengine: sh: usb-dmac: Use [] to denote a flexible array member dmaengine: dmatest: timeout value of -1 should specify infinite wait dmaengine: dw: Distinguish ->remove() between DW and iDMA 32-bit dmaengine: fsl-edma: support little endian for edma driver dmaengine: hsu: Revert "set HSU_CH_MTSR to memory width" dmagengine: pl330: add code to get reset property dt-bindings: pl330: document the optional resets property ...
160 lines
5.2 KiB
C
160 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Qualcomm Technologies HIDMA data structures
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*
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* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_HIDMA_H
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#define QCOM_HIDMA_H
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#include <linux/kfifo.h>
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#include <linux/interrupt.h>
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#include <linux/dmaengine.h>
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#define HIDMA_TRE_SIZE 32 /* each TRE is 32 bytes */
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#define HIDMA_TRE_CFG_IDX 0
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#define HIDMA_TRE_LEN_IDX 1
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#define HIDMA_TRE_SRC_LOW_IDX 2
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#define HIDMA_TRE_SRC_HI_IDX 3
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#define HIDMA_TRE_DEST_LOW_IDX 4
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#define HIDMA_TRE_DEST_HI_IDX 5
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enum tre_type {
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HIDMA_TRE_MEMCPY = 3,
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HIDMA_TRE_MEMSET = 4,
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};
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struct hidma_tre {
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atomic_t allocated; /* if this channel is allocated */
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bool queued; /* flag whether this is pending */
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u16 status; /* status */
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u32 idx; /* index of the tre */
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u32 dma_sig; /* signature of the tre */
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const char *dev_name; /* name of the device */
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void (*callback)(void *data); /* requester callback */
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void *data; /* Data associated with this channel*/
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struct hidma_lldev *lldev; /* lldma device pointer */
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u32 tre_local[HIDMA_TRE_SIZE / sizeof(u32) + 1]; /* TRE local copy */
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u32 tre_index; /* the offset where this was written*/
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u32 int_flags; /* interrupt flags */
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u8 err_info; /* error record in this transfer */
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u8 err_code; /* completion code */
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};
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struct hidma_lldev {
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bool msi_support; /* flag indicating MSI support */
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bool initialized; /* initialized flag */
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u8 trch_state; /* trch_state of the device */
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u8 evch_state; /* evch_state of the device */
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u8 chidx; /* channel index in the core */
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u32 nr_tres; /* max number of configs */
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spinlock_t lock; /* reentrancy */
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struct hidma_tre *trepool; /* trepool of user configs */
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struct device *dev; /* device */
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void __iomem *trca; /* Transfer Channel address */
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void __iomem *evca; /* Event Channel address */
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struct hidma_tre
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**pending_tre_list; /* Pointers to pending TREs */
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atomic_t pending_tre_count; /* Number of TREs pending */
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void *tre_ring; /* TRE ring */
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dma_addr_t tre_dma; /* TRE ring to be shared with HW */
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u32 tre_ring_size; /* Byte size of the ring */
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u32 tre_processed_off; /* last processed TRE */
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void *evre_ring; /* EVRE ring */
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dma_addr_t evre_dma; /* EVRE ring to be shared with HW */
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u32 evre_ring_size; /* Byte size of the ring */
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u32 evre_processed_off; /* last processed EVRE */
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u32 tre_write_offset; /* TRE write location */
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struct tasklet_struct task; /* task delivering notifications */
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DECLARE_KFIFO_PTR(handoff_fifo,
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struct hidma_tre *); /* pending TREs FIFO */
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};
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struct hidma_desc {
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struct dma_async_tx_descriptor desc;
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/* link list node for this channel*/
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struct list_head node;
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u32 tre_ch;
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};
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struct hidma_chan {
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bool paused;
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bool allocated;
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char dbg_name[16];
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u32 dma_sig;
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dma_cookie_t last_success;
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/*
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* active descriptor on this channel
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* It is used by the DMA complete notification to
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* locate the descriptor that initiated the transfer.
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*/
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struct hidma_dev *dmadev;
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struct hidma_desc *running;
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struct dma_chan chan;
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struct list_head free;
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struct list_head prepared;
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struct list_head queued;
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struct list_head active;
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struct list_head completed;
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/* Lock for this structure */
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spinlock_t lock;
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};
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struct hidma_dev {
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int irq;
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int chidx;
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u32 nr_descriptors;
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int msi_virqbase;
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struct hidma_lldev *lldev;
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void __iomem *dev_trca;
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struct resource *trca_resource;
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void __iomem *dev_evca;
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struct resource *evca_resource;
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/* used to protect the pending channel list*/
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spinlock_t lock;
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struct dma_device ddev;
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struct dentry *debugfs;
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/* sysfs entry for the channel id */
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struct device_attribute *chid_attrs;
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/* Task delivering issue_pending */
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struct tasklet_struct task;
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};
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int hidma_ll_request(struct hidma_lldev *llhndl, u32 dev_id,
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const char *dev_name,
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void (*callback)(void *data), void *data, u32 *tre_ch);
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void hidma_ll_free(struct hidma_lldev *llhndl, u32 tre_ch);
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enum dma_status hidma_ll_status(struct hidma_lldev *llhndl, u32 tre_ch);
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bool hidma_ll_isenabled(struct hidma_lldev *llhndl);
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void hidma_ll_queue_request(struct hidma_lldev *llhndl, u32 tre_ch);
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void hidma_ll_start(struct hidma_lldev *llhndl);
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int hidma_ll_disable(struct hidma_lldev *lldev);
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int hidma_ll_enable(struct hidma_lldev *llhndl);
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void hidma_ll_set_transfer_params(struct hidma_lldev *llhndl, u32 tre_ch,
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dma_addr_t src, dma_addr_t dest, u32 len, u32 flags, u32 txntype);
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void hidma_ll_setup_irq(struct hidma_lldev *lldev, bool msi);
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int hidma_ll_setup(struct hidma_lldev *lldev);
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struct hidma_lldev *hidma_ll_init(struct device *dev, u32 max_channels,
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void __iomem *trca, void __iomem *evca,
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u8 chidx);
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int hidma_ll_uninit(struct hidma_lldev *llhndl);
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irqreturn_t hidma_ll_inthandler(int irq, void *arg);
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irqreturn_t hidma_ll_inthandler_msi(int irq, void *arg, int cause);
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void hidma_cleanup_pending_tre(struct hidma_lldev *llhndl, u8 err_info,
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u8 err_code);
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void hidma_debug_init(struct hidma_dev *dmadev);
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void hidma_debug_uninit(struct hidma_dev *dmadev);
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#endif
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