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- Add support in dmaengine core to do device node checks for DT devices and update bunch of drivers to use that and remove open coding from drivers - New driver/driver support for new hardware, namely: - MediaTek UART APDMA - Freescale i.mx7ulp edma2 - Synopsys eDMA IP core version 0 - Allwinner H6 DMA - Updates to axi-dma and support for interleaved cyclic transfers - Greg's debugfs return value check removals on drivers - Updates to stm32-dma, hsu, dw, pl330, tegra drivers -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJdLKxYAAoJEHwUBw8lI4NHsH8P/AqYZpUlLthe5L4qItzM1Uf0 HqxsJYs0xworjSRml8uptx/TzjIgJnJfEk2PV5VA+0zJNz/HnH7lDH85wKDx1Ydl AatUuyAFRO3GZOup/hY0AEIPhoIMdg/3zS2aapjJmaEZCVK2eVKmcj0KMvO5g0cw tsmXm3O0xd2Na1ToslNyYgFfCn8ortuAeoKiXJxhivMbGjRfw4LW/RPgS17Vspvh mEuxNXFWAZ+DorgPF5BmDPZ+LXcGgCXGNIoj64W+VHaXU5yXnlky+6/0f7cEcFEd yl3hjXVwyAq5zIItIOmiuozZidi5yfoizXg4S2ZD3P4xXKZ5OZ9Gf/0SMyXUIErU pwGxo6ZgsBcEpAHtqySELQedttttID+jYYeWU6oDr2LOy3W3F7AHOEGg9l9ZllLh gRdIoz3PrMK1wy/9Ytl37xklZyBk+HJLkeoIAvjrNgNJ1YRKqcysUCwsmqO7SG3N HnIGx74sG8ChljT/yX5pElq3ip6qLdb4pJcsfxKJ9VSxsTZ3JNINGNQtvI19hKR/ 6sn/c1Rb5/S1WxINGr+2FxChxXF8OESCN6GIEu6mNYVBzQnNPzwgPxfAGCqdoOOH mqXXgYNePMaBGYXBkdgvP1CnqenRRmTYo/1L4QmI4Mve4xpd5zhx5cZt9FlQJ2Im /hVT8gZ6bIrutsVOy4rg =R+aC -----END PGP SIGNATURE----- Merge tag 'dmaengine-5.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma Pull dmaengine updates from Vinod Koul: - Add support in dmaengine core to do device node checks for DT devices and update bunch of drivers to use that and remove open coding from drivers - New driver/driver support for new hardware, namely: - MediaTek UART APDMA - Freescale i.mx7ulp edma2 - Synopsys eDMA IP core version 0 - Allwinner H6 DMA - Updates to axi-dma and support for interleaved cyclic transfers - Greg's debugfs return value check removals on drivers - Updates to stm32-dma, hsu, dw, pl330, tegra drivers * tag 'dmaengine-5.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (68 commits) dmaengine: Revert "dmaengine: fsl-edma: add i.mx7ulp edma2 version support" dmaengine: at_xdmac: check for non-empty xfers_list before invoking callback Documentation: dmaengine: clean up description of dmatest usage dmaengine: tegra210-adma: remove PM_CLK dependency dmaengine: fsl-edma: add i.mx7ulp edma2 version support dt-bindings: dma: fsl-edma: add new i.mx7ulp-edma dmaengine: fsl-edma-common: version check for v2 instead dmaengine: fsl-edma-common: move dmamux register to another single function dmaengine: fsl-edma: add drvdata for fsl-edma dmaengine: Revert "dmaengine: fsl-edma: support little endian for edma driver" dmaengine: rcar-dmac: Reject zero-length slave DMA requests dmaengine: dw: Enable iDMA 32-bit on Intel Elkhart Lake dmaengine: dw-edma: fix semicolon.cocci warnings dmaengine: sh: usb-dmac: Use [] to denote a flexible array member dmaengine: dmatest: timeout value of -1 should specify infinite wait dmaengine: dw: Distinguish ->remove() between DW and iDMA 32-bit dmaengine: fsl-edma: support little endian for edma driver dmaengine: hsu: Revert "set HSU_CH_MTSR to memory width" dmagengine: pl330: add code to get reset property dt-bindings: pl330: document the optional resets property ...
165 lines
5.3 KiB
C
165 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Qualcomm Technologies HIDMA debug file
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*
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* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
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*/
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#include <linux/debugfs.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/pm_runtime.h>
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#include "hidma.h"
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static void hidma_ll_chstats(struct seq_file *s, void *llhndl, u32 tre_ch)
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{
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struct hidma_lldev *lldev = llhndl;
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struct hidma_tre *tre;
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u32 length;
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dma_addr_t src_start;
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dma_addr_t dest_start;
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u32 *tre_local;
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if (tre_ch >= lldev->nr_tres) {
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dev_err(lldev->dev, "invalid TRE number in chstats:%d", tre_ch);
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return;
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}
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tre = &lldev->trepool[tre_ch];
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seq_printf(s, "------Channel %d -----\n", tre_ch);
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seq_printf(s, "allocated=%d\n", atomic_read(&tre->allocated));
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seq_printf(s, "queued = 0x%x\n", tre->queued);
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seq_printf(s, "err_info = 0x%x\n", tre->err_info);
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seq_printf(s, "err_code = 0x%x\n", tre->err_code);
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seq_printf(s, "status = 0x%x\n", tre->status);
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seq_printf(s, "idx = 0x%x\n", tre->idx);
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seq_printf(s, "dma_sig = 0x%x\n", tre->dma_sig);
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seq_printf(s, "dev_name=%s\n", tre->dev_name);
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seq_printf(s, "callback=%p\n", tre->callback);
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seq_printf(s, "data=%p\n", tre->data);
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seq_printf(s, "tre_index = 0x%x\n", tre->tre_index);
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tre_local = &tre->tre_local[0];
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src_start = tre_local[HIDMA_TRE_SRC_LOW_IDX];
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src_start = ((u64) (tre_local[HIDMA_TRE_SRC_HI_IDX]) << 32) + src_start;
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dest_start = tre_local[HIDMA_TRE_DEST_LOW_IDX];
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dest_start += ((u64) (tre_local[HIDMA_TRE_DEST_HI_IDX]) << 32);
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length = tre_local[HIDMA_TRE_LEN_IDX];
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seq_printf(s, "src=%pap\n", &src_start);
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seq_printf(s, "dest=%pap\n", &dest_start);
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seq_printf(s, "length = 0x%x\n", length);
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}
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static void hidma_ll_devstats(struct seq_file *s, void *llhndl)
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{
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struct hidma_lldev *lldev = llhndl;
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seq_puts(s, "------Device -----\n");
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seq_printf(s, "lldev init = 0x%x\n", lldev->initialized);
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seq_printf(s, "trch_state = 0x%x\n", lldev->trch_state);
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seq_printf(s, "evch_state = 0x%x\n", lldev->evch_state);
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seq_printf(s, "chidx = 0x%x\n", lldev->chidx);
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seq_printf(s, "nr_tres = 0x%x\n", lldev->nr_tres);
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seq_printf(s, "trca=%p\n", lldev->trca);
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seq_printf(s, "tre_ring=%p\n", lldev->tre_ring);
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seq_printf(s, "tre_ring_handle=%pap\n", &lldev->tre_dma);
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seq_printf(s, "tre_ring_size = 0x%x\n", lldev->tre_ring_size);
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seq_printf(s, "tre_processed_off = 0x%x\n", lldev->tre_processed_off);
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seq_printf(s, "pending_tre_count=%d\n",
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atomic_read(&lldev->pending_tre_count));
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seq_printf(s, "evca=%p\n", lldev->evca);
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seq_printf(s, "evre_ring=%p\n", lldev->evre_ring);
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seq_printf(s, "evre_ring_handle=%pap\n", &lldev->evre_dma);
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seq_printf(s, "evre_ring_size = 0x%x\n", lldev->evre_ring_size);
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seq_printf(s, "evre_processed_off = 0x%x\n", lldev->evre_processed_off);
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seq_printf(s, "tre_write_offset = 0x%x\n", lldev->tre_write_offset);
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}
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/*
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* hidma_chan_show: display HIDMA channel statistics
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*
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* Display the statistics for the current HIDMA virtual channel device.
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*/
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static int hidma_chan_show(struct seq_file *s, void *unused)
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{
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struct hidma_chan *mchan = s->private;
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struct hidma_desc *mdesc;
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struct hidma_dev *dmadev = mchan->dmadev;
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pm_runtime_get_sync(dmadev->ddev.dev);
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seq_printf(s, "paused=%u\n", mchan->paused);
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seq_printf(s, "dma_sig=%u\n", mchan->dma_sig);
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seq_puts(s, "prepared\n");
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list_for_each_entry(mdesc, &mchan->prepared, node)
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hidma_ll_chstats(s, mchan->dmadev->lldev, mdesc->tre_ch);
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seq_puts(s, "active\n");
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list_for_each_entry(mdesc, &mchan->active, node)
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hidma_ll_chstats(s, mchan->dmadev->lldev, mdesc->tre_ch);
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seq_puts(s, "completed\n");
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list_for_each_entry(mdesc, &mchan->completed, node)
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hidma_ll_chstats(s, mchan->dmadev->lldev, mdesc->tre_ch);
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hidma_ll_devstats(s, mchan->dmadev->lldev);
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pm_runtime_mark_last_busy(dmadev->ddev.dev);
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pm_runtime_put_autosuspend(dmadev->ddev.dev);
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return 0;
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}
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/*
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* hidma_dma_show: display HIDMA device info
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*
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* Display the info for the current HIDMA device.
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*/
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static int hidma_dma_show(struct seq_file *s, void *unused)
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{
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struct hidma_dev *dmadev = s->private;
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resource_size_t sz;
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seq_printf(s, "nr_descriptors=%d\n", dmadev->nr_descriptors);
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seq_printf(s, "dev_trca=%p\n", &dmadev->dev_trca);
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seq_printf(s, "dev_trca_phys=%pa\n", &dmadev->trca_resource->start);
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sz = resource_size(dmadev->trca_resource);
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seq_printf(s, "dev_trca_size=%pa\n", &sz);
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seq_printf(s, "dev_evca=%p\n", &dmadev->dev_evca);
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seq_printf(s, "dev_evca_phys=%pa\n", &dmadev->evca_resource->start);
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sz = resource_size(dmadev->evca_resource);
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seq_printf(s, "dev_evca_size=%pa\n", &sz);
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(hidma_chan);
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DEFINE_SHOW_ATTRIBUTE(hidma_dma);
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void hidma_debug_uninit(struct hidma_dev *dmadev)
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{
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debugfs_remove_recursive(dmadev->debugfs);
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}
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void hidma_debug_init(struct hidma_dev *dmadev)
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{
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int chidx = 0;
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struct list_head *position = NULL;
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struct dentry *dir;
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dmadev->debugfs = debugfs_create_dir(dev_name(dmadev->ddev.dev), NULL);
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/* walk through the virtual channel list */
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list_for_each(position, &dmadev->ddev.channels) {
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struct hidma_chan *chan;
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chan = list_entry(position, struct hidma_chan,
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chan.device_node);
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sprintf(chan->dbg_name, "chan%d", chidx);
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dir = debugfs_create_dir(chan->dbg_name,
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dmadev->debugfs);
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debugfs_create_file("stats", S_IRUGO, dir, chan,
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&hidma_chan_fops);
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chidx++;
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}
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debugfs_create_file("stats", S_IRUGO, dmadev->debugfs, dmadev,
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&hidma_dma_fops);
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}
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