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![Phillip Potter](/assets/img/avatar_default.png)
Place a comment in hidma_mgmt_init explaining why success must currently be assumed, due to the cleanup issue that would need to be considered were this module ever to be unloadable or were this platform_driver_register call ever to fail. Acked-By: Vinod Koul <vkoul@kernel.org> Acked-By: Sinan Kaya <okaya@kernel.org> Signed-off-by: Phillip Potter <phil@philpotter.co.uk> Link: https://lore.kernel.org/r/20210503115736.2104747-52-gregkh@linuxfoundation.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
440 lines
12 KiB
C
440 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Qualcomm Technologies HIDMA DMA engine Management interface
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*
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* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
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*/
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#include <linux/dmaengine.h>
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#include <linux/acpi.h>
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#include <linux/of.h>
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#include <linux/property.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/module.h>
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#include <linux/uaccess.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <linux/bitops.h>
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#include <linux/dma-mapping.h>
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#include "hidma_mgmt.h"
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#define HIDMA_QOS_N_OFFSET 0x700
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#define HIDMA_CFG_OFFSET 0x400
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#define HIDMA_MAX_BUS_REQ_LEN_OFFSET 0x41C
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#define HIDMA_MAX_XACTIONS_OFFSET 0x420
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#define HIDMA_HW_VERSION_OFFSET 0x424
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#define HIDMA_CHRESET_TIMEOUT_OFFSET 0x418
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#define HIDMA_MAX_WR_XACTIONS_MASK GENMASK(4, 0)
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#define HIDMA_MAX_RD_XACTIONS_MASK GENMASK(4, 0)
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#define HIDMA_WEIGHT_MASK GENMASK(6, 0)
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#define HIDMA_MAX_BUS_REQ_LEN_MASK GENMASK(15, 0)
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#define HIDMA_CHRESET_TIMEOUT_MASK GENMASK(19, 0)
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#define HIDMA_MAX_WR_XACTIONS_BIT_POS 16
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#define HIDMA_MAX_BUS_WR_REQ_BIT_POS 16
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#define HIDMA_WRR_BIT_POS 8
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#define HIDMA_PRIORITY_BIT_POS 15
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#define HIDMA_AUTOSUSPEND_TIMEOUT 2000
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#define HIDMA_MAX_CHANNEL_WEIGHT 15
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static unsigned int max_write_request;
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module_param(max_write_request, uint, 0644);
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MODULE_PARM_DESC(max_write_request,
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"maximum write burst (default: ACPI/DT value)");
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static unsigned int max_read_request;
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module_param(max_read_request, uint, 0644);
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MODULE_PARM_DESC(max_read_request,
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"maximum read burst (default: ACPI/DT value)");
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static unsigned int max_wr_xactions;
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module_param(max_wr_xactions, uint, 0644);
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MODULE_PARM_DESC(max_wr_xactions,
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"maximum number of write transactions (default: ACPI/DT value)");
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static unsigned int max_rd_xactions;
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module_param(max_rd_xactions, uint, 0644);
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MODULE_PARM_DESC(max_rd_xactions,
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"maximum number of read transactions (default: ACPI/DT value)");
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int hidma_mgmt_setup(struct hidma_mgmt_dev *mgmtdev)
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{
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unsigned int i;
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u32 val;
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if (!is_power_of_2(mgmtdev->max_write_request) ||
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(mgmtdev->max_write_request < 128) ||
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(mgmtdev->max_write_request > 1024)) {
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dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n",
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mgmtdev->max_write_request);
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return -EINVAL;
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}
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if (!is_power_of_2(mgmtdev->max_read_request) ||
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(mgmtdev->max_read_request < 128) ||
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(mgmtdev->max_read_request > 1024)) {
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dev_err(&mgmtdev->pdev->dev, "invalid read request %d\n",
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mgmtdev->max_read_request);
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return -EINVAL;
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}
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if (mgmtdev->max_wr_xactions > HIDMA_MAX_WR_XACTIONS_MASK) {
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dev_err(&mgmtdev->pdev->dev,
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"max_wr_xactions cannot be bigger than %ld\n",
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HIDMA_MAX_WR_XACTIONS_MASK);
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return -EINVAL;
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}
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if (mgmtdev->max_rd_xactions > HIDMA_MAX_RD_XACTIONS_MASK) {
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dev_err(&mgmtdev->pdev->dev,
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"max_rd_xactions cannot be bigger than %ld\n",
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HIDMA_MAX_RD_XACTIONS_MASK);
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return -EINVAL;
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}
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for (i = 0; i < mgmtdev->dma_channels; i++) {
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if (mgmtdev->priority[i] > 1) {
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dev_err(&mgmtdev->pdev->dev,
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"priority can be 0 or 1\n");
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return -EINVAL;
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}
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if (mgmtdev->weight[i] > HIDMA_MAX_CHANNEL_WEIGHT) {
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dev_err(&mgmtdev->pdev->dev,
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"max value of weight can be %d.\n",
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HIDMA_MAX_CHANNEL_WEIGHT);
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return -EINVAL;
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}
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/* weight needs to be at least one */
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if (mgmtdev->weight[i] == 0)
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mgmtdev->weight[i] = 1;
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}
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pm_runtime_get_sync(&mgmtdev->pdev->dev);
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val = readl(mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
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val &= ~(HIDMA_MAX_BUS_REQ_LEN_MASK << HIDMA_MAX_BUS_WR_REQ_BIT_POS);
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val |= mgmtdev->max_write_request << HIDMA_MAX_BUS_WR_REQ_BIT_POS;
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val &= ~HIDMA_MAX_BUS_REQ_LEN_MASK;
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val |= mgmtdev->max_read_request;
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writel(val, mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
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val = readl(mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
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val &= ~(HIDMA_MAX_WR_XACTIONS_MASK << HIDMA_MAX_WR_XACTIONS_BIT_POS);
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val |= mgmtdev->max_wr_xactions << HIDMA_MAX_WR_XACTIONS_BIT_POS;
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val &= ~HIDMA_MAX_RD_XACTIONS_MASK;
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val |= mgmtdev->max_rd_xactions;
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writel(val, mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
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mgmtdev->hw_version =
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readl(mgmtdev->virtaddr + HIDMA_HW_VERSION_OFFSET);
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mgmtdev->hw_version_major = (mgmtdev->hw_version >> 28) & 0xF;
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mgmtdev->hw_version_minor = (mgmtdev->hw_version >> 16) & 0xF;
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for (i = 0; i < mgmtdev->dma_channels; i++) {
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u32 weight = mgmtdev->weight[i];
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u32 priority = mgmtdev->priority[i];
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val = readl(mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
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val &= ~(1 << HIDMA_PRIORITY_BIT_POS);
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val |= (priority & 0x1) << HIDMA_PRIORITY_BIT_POS;
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val &= ~(HIDMA_WEIGHT_MASK << HIDMA_WRR_BIT_POS);
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val |= (weight & HIDMA_WEIGHT_MASK) << HIDMA_WRR_BIT_POS;
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writel(val, mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
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}
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val = readl(mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
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val &= ~HIDMA_CHRESET_TIMEOUT_MASK;
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val |= mgmtdev->chreset_timeout_cycles & HIDMA_CHRESET_TIMEOUT_MASK;
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writel(val, mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
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pm_runtime_mark_last_busy(&mgmtdev->pdev->dev);
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pm_runtime_put_autosuspend(&mgmtdev->pdev->dev);
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return 0;
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}
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EXPORT_SYMBOL_GPL(hidma_mgmt_setup);
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static int hidma_mgmt_probe(struct platform_device *pdev)
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{
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struct hidma_mgmt_dev *mgmtdev;
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struct resource *res;
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void __iomem *virtaddr;
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int irq;
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int rc;
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u32 val;
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pm_runtime_set_autosuspend_delay(&pdev->dev, HIDMA_AUTOSUSPEND_TIMEOUT);
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pm_runtime_use_autosuspend(&pdev->dev);
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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pm_runtime_get_sync(&pdev->dev);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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virtaddr = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(virtaddr)) {
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rc = -ENOMEM;
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goto out;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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rc = irq;
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goto out;
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}
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mgmtdev = devm_kzalloc(&pdev->dev, sizeof(*mgmtdev), GFP_KERNEL);
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if (!mgmtdev) {
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rc = -ENOMEM;
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goto out;
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}
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mgmtdev->pdev = pdev;
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mgmtdev->addrsize = resource_size(res);
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mgmtdev->virtaddr = virtaddr;
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rc = device_property_read_u32(&pdev->dev, "dma-channels",
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&mgmtdev->dma_channels);
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if (rc) {
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dev_err(&pdev->dev, "number of channels missing\n");
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goto out;
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}
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rc = device_property_read_u32(&pdev->dev,
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"channel-reset-timeout-cycles",
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&mgmtdev->chreset_timeout_cycles);
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if (rc) {
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dev_err(&pdev->dev, "channel reset timeout missing\n");
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goto out;
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}
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rc = device_property_read_u32(&pdev->dev, "max-write-burst-bytes",
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&mgmtdev->max_write_request);
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if (rc) {
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dev_err(&pdev->dev, "max-write-burst-bytes missing\n");
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goto out;
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}
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if (max_write_request &&
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(max_write_request != mgmtdev->max_write_request)) {
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dev_info(&pdev->dev, "overriding max-write-burst-bytes: %d\n",
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max_write_request);
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mgmtdev->max_write_request = max_write_request;
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} else
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max_write_request = mgmtdev->max_write_request;
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rc = device_property_read_u32(&pdev->dev, "max-read-burst-bytes",
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&mgmtdev->max_read_request);
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if (rc) {
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dev_err(&pdev->dev, "max-read-burst-bytes missing\n");
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goto out;
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}
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if (max_read_request &&
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(max_read_request != mgmtdev->max_read_request)) {
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dev_info(&pdev->dev, "overriding max-read-burst-bytes: %d\n",
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max_read_request);
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mgmtdev->max_read_request = max_read_request;
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} else
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max_read_request = mgmtdev->max_read_request;
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rc = device_property_read_u32(&pdev->dev, "max-write-transactions",
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&mgmtdev->max_wr_xactions);
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if (rc) {
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dev_err(&pdev->dev, "max-write-transactions missing\n");
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goto out;
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}
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if (max_wr_xactions &&
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(max_wr_xactions != mgmtdev->max_wr_xactions)) {
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dev_info(&pdev->dev, "overriding max-write-transactions: %d\n",
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max_wr_xactions);
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mgmtdev->max_wr_xactions = max_wr_xactions;
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} else
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max_wr_xactions = mgmtdev->max_wr_xactions;
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rc = device_property_read_u32(&pdev->dev, "max-read-transactions",
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&mgmtdev->max_rd_xactions);
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if (rc) {
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dev_err(&pdev->dev, "max-read-transactions missing\n");
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goto out;
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}
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if (max_rd_xactions &&
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(max_rd_xactions != mgmtdev->max_rd_xactions)) {
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dev_info(&pdev->dev, "overriding max-read-transactions: %d\n",
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max_rd_xactions);
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mgmtdev->max_rd_xactions = max_rd_xactions;
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} else
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max_rd_xactions = mgmtdev->max_rd_xactions;
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mgmtdev->priority = devm_kcalloc(&pdev->dev,
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mgmtdev->dma_channels,
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sizeof(*mgmtdev->priority),
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GFP_KERNEL);
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if (!mgmtdev->priority) {
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rc = -ENOMEM;
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goto out;
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}
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mgmtdev->weight = devm_kcalloc(&pdev->dev,
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mgmtdev->dma_channels,
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sizeof(*mgmtdev->weight), GFP_KERNEL);
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if (!mgmtdev->weight) {
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rc = -ENOMEM;
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goto out;
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}
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rc = hidma_mgmt_setup(mgmtdev);
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if (rc) {
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dev_err(&pdev->dev, "setup failed\n");
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goto out;
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}
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/* start the HW */
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val = readl(mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
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val |= 1;
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writel(val, mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
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rc = hidma_mgmt_init_sys(mgmtdev);
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if (rc) {
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dev_err(&pdev->dev, "sysfs setup failed\n");
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goto out;
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}
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dev_info(&pdev->dev,
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"HW rev: %d.%d @ %pa with %d physical channels\n",
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mgmtdev->hw_version_major, mgmtdev->hw_version_minor,
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&res->start, mgmtdev->dma_channels);
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platform_set_drvdata(pdev, mgmtdev);
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pm_runtime_mark_last_busy(&pdev->dev);
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pm_runtime_put_autosuspend(&pdev->dev);
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return 0;
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out:
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pm_runtime_put_sync_suspend(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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return rc;
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}
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#if IS_ENABLED(CONFIG_ACPI)
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static const struct acpi_device_id hidma_mgmt_acpi_ids[] = {
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{"QCOM8060"},
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{},
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};
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MODULE_DEVICE_TABLE(acpi, hidma_mgmt_acpi_ids);
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#endif
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static const struct of_device_id hidma_mgmt_match[] = {
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{.compatible = "qcom,hidma-mgmt-1.0",},
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{},
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};
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MODULE_DEVICE_TABLE(of, hidma_mgmt_match);
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static struct platform_driver hidma_mgmt_driver = {
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.probe = hidma_mgmt_probe,
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.driver = {
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.name = "hidma-mgmt",
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.of_match_table = hidma_mgmt_match,
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.acpi_match_table = ACPI_PTR(hidma_mgmt_acpi_ids),
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},
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};
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#if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
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static int object_counter;
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static int __init hidma_mgmt_of_populate_channels(struct device_node *np)
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{
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struct platform_device *pdev_parent = of_find_device_by_node(np);
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struct platform_device_info pdevinfo;
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struct device_node *child;
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struct resource *res;
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int ret = 0;
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/* allocate a resource array */
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res = kcalloc(3, sizeof(*res), GFP_KERNEL);
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if (!res)
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return -ENOMEM;
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for_each_available_child_of_node(np, child) {
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struct platform_device *new_pdev;
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ret = of_address_to_resource(child, 0, &res[0]);
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if (!ret)
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goto out;
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ret = of_address_to_resource(child, 1, &res[1]);
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if (!ret)
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goto out;
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ret = of_irq_to_resource(child, 0, &res[2]);
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if (ret <= 0)
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goto out;
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memset(&pdevinfo, 0, sizeof(pdevinfo));
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pdevinfo.fwnode = &child->fwnode;
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pdevinfo.parent = pdev_parent ? &pdev_parent->dev : NULL;
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pdevinfo.name = child->name;
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pdevinfo.id = object_counter++;
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pdevinfo.res = res;
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pdevinfo.num_res = 3;
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pdevinfo.data = NULL;
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pdevinfo.size_data = 0;
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pdevinfo.dma_mask = DMA_BIT_MASK(64);
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new_pdev = platform_device_register_full(&pdevinfo);
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if (IS_ERR(new_pdev)) {
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ret = PTR_ERR(new_pdev);
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goto out;
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}
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new_pdev->dev.of_node = child;
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of_dma_configure(&new_pdev->dev, child, true);
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/*
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* It is assumed that calling of_msi_configure is safe on
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* platforms with or without MSI support.
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*/
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of_msi_configure(&new_pdev->dev, child);
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}
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kfree(res);
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return ret;
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out:
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of_node_put(child);
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kfree(res);
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return ret;
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}
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#endif
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static int __init hidma_mgmt_init(void)
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{
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#if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
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struct device_node *child;
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for_each_matching_node(child, hidma_mgmt_match) {
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/* device tree based firmware here */
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hidma_mgmt_of_populate_channels(child);
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}
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#endif
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/*
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* We do not check for return value here, as it is assumed that
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* platform_driver_register must not fail. The reason for this is that
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* the (potential) hidma_mgmt_of_populate_channels calls above are not
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* cleaned up if it does fail, and to do this work is quite
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* complicated. In particular, various calls of of_address_to_resource,
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* of_irq_to_resource, platform_device_register_full, of_dma_configure,
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* and of_msi_configure which then call other functions and so on, must
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* be cleaned up - this is not a trivial exercise.
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*
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* Currently, this module is not intended to be unloaded, and there is
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* no module_exit function defined which does the needed cleanup. For
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* this reason, we have to assume success here.
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*/
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platform_driver_register(&hidma_mgmt_driver);
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return 0;
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}
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module_init(hidma_mgmt_init);
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MODULE_LICENSE("GPL v2");
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