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![Alexandru Tachici](/assets/img/avatar_default.png)
Currently AD7124-8 driver cannot use more than 8 IIO channels because it was assigning the channel configurations bijectively to channels specified in the device-tree. This is not possible to do when using more than 8 channels as AD7124-8 has only 8 configuration registers. To allow the user to use all channels at once the driver will keep in memory configurations for all channels but will program only 8 of them at a time on the device. If multiple channels have the same configuration, only one configuration register will be used. If there are more configurations than available registers only the last 8 used configurations will be allowed to exist on the device in a LRU fashion. Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com> Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20210311091154.47785-2-alexandru.tachici@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
986 lines
24 KiB
C
986 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* AD7124 SPI ADC driver
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*
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* Copyright 2018 Analog Devices Inc.
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/kfifo.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/spi/spi.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/adc/ad_sigma_delta.h>
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#include <linux/iio/sysfs.h>
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/* AD7124 registers */
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#define AD7124_COMMS 0x00
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#define AD7124_STATUS 0x00
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#define AD7124_ADC_CONTROL 0x01
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#define AD7124_DATA 0x02
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#define AD7124_IO_CONTROL_1 0x03
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#define AD7124_IO_CONTROL_2 0x04
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#define AD7124_ID 0x05
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#define AD7124_ERROR 0x06
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#define AD7124_ERROR_EN 0x07
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#define AD7124_MCLK_COUNT 0x08
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#define AD7124_CHANNEL(x) (0x09 + (x))
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#define AD7124_CONFIG(x) (0x19 + (x))
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#define AD7124_FILTER(x) (0x21 + (x))
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#define AD7124_OFFSET(x) (0x29 + (x))
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#define AD7124_GAIN(x) (0x31 + (x))
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/* AD7124_STATUS */
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#define AD7124_STATUS_POR_FLAG_MSK BIT(4)
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/* AD7124_ADC_CONTROL */
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#define AD7124_ADC_CTRL_REF_EN_MSK BIT(8)
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#define AD7124_ADC_CTRL_REF_EN(x) FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
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#define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
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#define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
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#define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2)
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#define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
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/* AD7124 ID */
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#define AD7124_DEVICE_ID_MSK GENMASK(7, 4)
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#define AD7124_DEVICE_ID_GET(x) FIELD_GET(AD7124_DEVICE_ID_MSK, x)
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#define AD7124_SILICON_REV_MSK GENMASK(3, 0)
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#define AD7124_SILICON_REV_GET(x) FIELD_GET(AD7124_SILICON_REV_MSK, x)
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#define CHIPID_AD7124_4 0x0
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#define CHIPID_AD7124_8 0x1
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/* AD7124_CHANNEL_X */
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#define AD7124_CHANNEL_EN_MSK BIT(15)
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#define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
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#define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12)
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#define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
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#define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
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#define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
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#define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
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#define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
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/* AD7124_CONFIG_X */
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#define AD7124_CONFIG_BIPOLAR_MSK BIT(11)
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#define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
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#define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3)
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#define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
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#define AD7124_CONFIG_PGA_MSK GENMASK(2, 0)
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#define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
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#define AD7124_CONFIG_IN_BUFF_MSK GENMASK(7, 6)
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#define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
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/* AD7124_FILTER_X */
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#define AD7124_FILTER_FS_MSK GENMASK(10, 0)
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#define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x)
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#define AD7124_FILTER_TYPE_MSK GENMASK(23, 21)
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#define AD7124_FILTER_TYPE_SEL(x) FIELD_PREP(AD7124_FILTER_TYPE_MSK, x)
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#define AD7124_SINC3_FILTER 2
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#define AD7124_SINC4_FILTER 0
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#define AD7124_CONF_ADDR_OFFSET 20
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#define AD7124_MAX_CONFIGS 8
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#define AD7124_MAX_CHANNELS 16
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enum ad7124_ids {
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ID_AD7124_4,
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ID_AD7124_8,
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};
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enum ad7124_ref_sel {
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AD7124_REFIN1,
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AD7124_REFIN2,
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AD7124_INT_REF,
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AD7124_AVDD_REF,
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};
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enum ad7124_power_mode {
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AD7124_LOW_POWER,
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AD7124_MID_POWER,
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AD7124_FULL_POWER,
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};
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static const unsigned int ad7124_gain[8] = {
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1, 2, 4, 8, 16, 32, 64, 128
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};
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static const unsigned int ad7124_reg_size[] = {
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1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3
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};
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static const int ad7124_master_clk_freq_hz[3] = {
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[AD7124_LOW_POWER] = 76800,
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[AD7124_MID_POWER] = 153600,
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[AD7124_FULL_POWER] = 614400,
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};
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static const char * const ad7124_ref_names[] = {
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[AD7124_REFIN1] = "refin1",
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[AD7124_REFIN2] = "refin2",
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[AD7124_INT_REF] = "int",
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[AD7124_AVDD_REF] = "avdd",
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};
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struct ad7124_chip_info {
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const char *name;
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unsigned int chip_id;
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unsigned int num_inputs;
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};
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struct ad7124_channel_config {
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bool live;
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unsigned int cfg_slot;
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enum ad7124_ref_sel refsel;
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bool bipolar;
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bool buf_positive;
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bool buf_negative;
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unsigned int vref_mv;
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unsigned int pga_bits;
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unsigned int odr;
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unsigned int odr_sel_bits;
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unsigned int filter_type;
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};
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struct ad7124_channel {
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unsigned int nr;
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struct ad7124_channel_config cfg;
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unsigned int ain;
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unsigned int slot;
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};
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struct ad7124_state {
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const struct ad7124_chip_info *chip_info;
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struct ad_sigma_delta sd;
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struct ad7124_channel *channels;
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struct regulator *vref[4];
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struct clk *mclk;
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unsigned int adc_control;
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unsigned int num_channels;
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struct mutex cfgs_lock; /* lock for configs access */
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unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */
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DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS);
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};
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static const struct iio_chan_spec ad7124_channel_template = {
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.type = IIO_VOLTAGE,
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.indexed = 1,
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.differential = 1,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
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BIT(IIO_CHAN_INFO_SCALE) |
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BIT(IIO_CHAN_INFO_OFFSET) |
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BIT(IIO_CHAN_INFO_SAMP_FREQ) |
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BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
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.scan_type = {
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.sign = 'u',
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.realbits = 24,
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.storagebits = 32,
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.shift = 8,
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.endianness = IIO_BE,
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},
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};
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static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
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[ID_AD7124_4] = {
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.name = "ad7124-4",
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.chip_id = CHIPID_AD7124_4,
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.num_inputs = 8,
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},
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[ID_AD7124_8] = {
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.name = "ad7124-8",
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.chip_id = CHIPID_AD7124_8,
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.num_inputs = 16,
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},
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};
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static int ad7124_find_closest_match(const int *array,
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unsigned int size, int val)
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{
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int i, idx;
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unsigned int diff_new, diff_old;
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diff_old = U32_MAX;
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idx = 0;
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for (i = 0; i < size; i++) {
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diff_new = abs(val - array[i]);
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if (diff_new < diff_old) {
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diff_old = diff_new;
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idx = i;
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}
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}
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return idx;
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}
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static int ad7124_spi_write_mask(struct ad7124_state *st,
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unsigned int addr,
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unsigned long mask,
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unsigned int val,
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unsigned int bytes)
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{
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unsigned int readval;
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int ret;
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ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
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if (ret < 0)
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return ret;
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readval &= ~mask;
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readval |= val;
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return ad_sd_write_reg(&st->sd, addr, bytes, readval);
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}
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static int ad7124_set_mode(struct ad_sigma_delta *sd,
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enum ad_sigma_delta_mode mode)
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{
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struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
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st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
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st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
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return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
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}
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static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr)
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{
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unsigned int fclk, odr_sel_bits;
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fclk = clk_get_rate(st->mclk);
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/*
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* FS[10:0] = fCLK / (fADC x 32) where:
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* fADC is the output data rate
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* fCLK is the master clock frequency
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* FS[10:0] are the bits in the filter register
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* FS[10:0] can have a value from 1 to 2047
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*/
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odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
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if (odr_sel_bits < 1)
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odr_sel_bits = 1;
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else if (odr_sel_bits > 2047)
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odr_sel_bits = 2047;
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if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits)
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st->channels[channel].cfg.live = false;
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/* fADC = fCLK / (FS[10:0] x 32) */
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st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
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st->channels[channel].cfg.odr_sel_bits = odr_sel_bits;
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}
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static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
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unsigned int channel)
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{
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unsigned int fadc;
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fadc = st->channels[channel].cfg.odr;
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switch (st->channels[channel].cfg.filter_type) {
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case AD7124_SINC3_FILTER:
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return DIV_ROUND_CLOSEST(fadc * 230, 1000);
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case AD7124_SINC4_FILTER:
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return DIV_ROUND_CLOSEST(fadc * 262, 1000);
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default:
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return -EINVAL;
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}
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}
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static void ad7124_set_3db_filter_freq(struct ad7124_state *st, unsigned int channel,
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unsigned int freq)
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{
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unsigned int sinc4_3db_odr;
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unsigned int sinc3_3db_odr;
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unsigned int new_filter;
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unsigned int new_odr;
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sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230);
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sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262);
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if (sinc4_3db_odr > sinc3_3db_odr) {
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new_filter = AD7124_SINC3_FILTER;
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new_odr = sinc4_3db_odr;
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} else {
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new_filter = AD7124_SINC4_FILTER;
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new_odr = sinc3_3db_odr;
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}
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if (new_odr != st->channels[channel].cfg.odr)
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st->channels[channel].cfg.live = false;
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st->channels[channel].cfg.filter_type = new_filter;
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st->channels[channel].cfg.odr = new_odr;
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}
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static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st,
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struct ad7124_channel_config *cfg)
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{
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struct ad7124_channel_config *cfg_aux;
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ptrdiff_t cmp_size;
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int i;
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cmp_size = (u8 *)&cfg->live - (u8 *)cfg;
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for (i = 0; i < st->num_channels; i++) {
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cfg_aux = &st->channels[i].cfg;
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if (cfg_aux->live && !memcmp(cfg, cfg_aux, cmp_size))
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return cfg_aux;
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}
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return NULL;
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}
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static int ad7124_find_free_config_slot(struct ad7124_state *st)
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{
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unsigned int free_cfg_slot;
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free_cfg_slot = find_next_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS, 0);
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if (free_cfg_slot == AD7124_MAX_CONFIGS)
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return -1;
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return free_cfg_slot;
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}
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static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg)
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{
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unsigned int refsel = cfg->refsel;
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switch (refsel) {
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case AD7124_REFIN1:
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case AD7124_REFIN2:
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case AD7124_AVDD_REF:
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if (IS_ERR(st->vref[refsel])) {
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dev_err(&st->sd.spi->dev,
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"Error, trying to use external voltage reference without a %s regulator.\n",
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ad7124_ref_names[refsel]);
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return PTR_ERR(st->vref[refsel]);
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}
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cfg->vref_mv = regulator_get_voltage(st->vref[refsel]);
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/* Conversion from uV to mV */
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cfg->vref_mv /= 1000;
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return 0;
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case AD7124_INT_REF:
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cfg->vref_mv = 2500;
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st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
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st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
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return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL,
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2, st->adc_control);
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default:
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dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
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return -EINVAL;
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}
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}
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static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg,
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unsigned int cfg_slot)
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{
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unsigned int tmp;
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unsigned int val;
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int ret;
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cfg->cfg_slot = cfg_slot;
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tmp = (cfg->buf_positive << 1) + cfg->buf_negative;
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val = AD7124_CONFIG_BIPOLAR(cfg->bipolar) | AD7124_CONFIG_REF_SEL(cfg->refsel) |
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AD7124_CONFIG_IN_BUFF(tmp);
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ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val);
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if (ret < 0)
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return ret;
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tmp = AD7124_FILTER_TYPE_SEL(cfg->filter_type);
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ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_TYPE_MSK,
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tmp, 3);
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if (ret < 0)
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return ret;
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ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_FS_MSK,
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AD7124_FILTER_FS(cfg->odr_sel_bits), 3);
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if (ret < 0)
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return ret;
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return ad7124_spi_write_mask(st, AD7124_CONFIG(cfg->cfg_slot), AD7124_CONFIG_PGA_MSK,
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AD7124_CONFIG_PGA(cfg->pga_bits), 2);
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}
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static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st)
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{
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struct ad7124_channel_config *lru_cfg;
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struct ad7124_channel_config *cfg;
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int ret;
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int i;
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/*
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* Pop least recently used config from the fifo
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* in order to make room for the new one
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*/
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ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg);
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if (ret <= 0)
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return NULL;
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lru_cfg->live = false;
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/* mark slot as free */
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assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0);
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/* invalidate all other configs that pointed to this one */
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|
for (i = 0; i < st->num_channels; i++) {
|
|
cfg = &st->channels[i].cfg;
|
|
|
|
if (cfg->cfg_slot == lru_cfg->cfg_slot)
|
|
cfg->live = false;
|
|
}
|
|
|
|
return lru_cfg;
|
|
}
|
|
|
|
static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg)
|
|
{
|
|
struct ad7124_channel_config *lru_cfg;
|
|
int free_cfg_slot;
|
|
|
|
free_cfg_slot = ad7124_find_free_config_slot(st);
|
|
if (free_cfg_slot >= 0) {
|
|
/* push the new config in configs queue */
|
|
kfifo_put(&st->live_cfgs_fifo, cfg);
|
|
} else {
|
|
/* pop one config to make room for the new one */
|
|
lru_cfg = ad7124_pop_config(st);
|
|
if (!lru_cfg)
|
|
return -EINVAL;
|
|
|
|
/* push the new config in configs queue */
|
|
free_cfg_slot = lru_cfg->cfg_slot;
|
|
kfifo_put(&st->live_cfgs_fifo, cfg);
|
|
}
|
|
|
|
/* mark slot as used */
|
|
assign_bit(free_cfg_slot, &st->cfg_slots_status, 1);
|
|
|
|
return ad7124_write_config(st, cfg, free_cfg_slot);
|
|
}
|
|
|
|
static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch)
|
|
{
|
|
ch->cfg.live = true;
|
|
return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain |
|
|
AD7124_CHANNEL_SETUP(ch->cfg.cfg_slot) | AD7124_CHANNEL_EN(1));
|
|
}
|
|
|
|
static int ad7124_prepare_read(struct ad7124_state *st, int address)
|
|
{
|
|
struct ad7124_channel_config *cfg = &st->channels[address].cfg;
|
|
struct ad7124_channel_config *live_cfg;
|
|
|
|
/*
|
|
* Before doing any reads assign the channel a configuration.
|
|
* Check if channel's config is on the device
|
|
*/
|
|
if (!cfg->live) {
|
|
/* check if config matches another one */
|
|
live_cfg = ad7124_find_similar_live_cfg(st, cfg);
|
|
if (!live_cfg)
|
|
ad7124_push_config(st, cfg);
|
|
else
|
|
cfg->cfg_slot = live_cfg->cfg_slot;
|
|
}
|
|
|
|
/* point channel to the config slot and enable */
|
|
return ad7124_enable_channel(st, &st->channels[address]);
|
|
}
|
|
|
|
static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
|
|
{
|
|
struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
|
|
int ret;
|
|
|
|
mutex_lock(&st->cfgs_lock);
|
|
ret = ad7124_prepare_read(st, channel);
|
|
mutex_unlock(&st->cfgs_lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
|
|
.set_channel = ad7124_set_channel,
|
|
.set_mode = ad7124_set_mode,
|
|
.has_registers = true,
|
|
.addr_shift = 0,
|
|
.read_mask = BIT(6),
|
|
.data_reg = AD7124_DATA,
|
|
.irq_flags = IRQF_TRIGGER_FALLING
|
|
};
|
|
|
|
static int ad7124_read_raw(struct iio_dev *indio_dev,
|
|
struct iio_chan_spec const *chan,
|
|
int *val, int *val2, long info)
|
|
{
|
|
struct ad7124_state *st = iio_priv(indio_dev);
|
|
int idx, ret;
|
|
|
|
switch (info) {
|
|
case IIO_CHAN_INFO_RAW:
|
|
ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* After the conversion is performed, disable the channel */
|
|
ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(chan->address), 2,
|
|
st->channels[chan->address].ain | AD7124_CHANNEL_EN(0));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return IIO_VAL_INT;
|
|
case IIO_CHAN_INFO_SCALE:
|
|
mutex_lock(&st->cfgs_lock);
|
|
|
|
idx = st->channels[chan->address].cfg.pga_bits;
|
|
*val = st->channels[chan->address].cfg.vref_mv;
|
|
if (st->channels[chan->address].cfg.bipolar)
|
|
*val2 = chan->scan_type.realbits - 1 + idx;
|
|
else
|
|
*val2 = chan->scan_type.realbits + idx;
|
|
|
|
mutex_unlock(&st->cfgs_lock);
|
|
return IIO_VAL_FRACTIONAL_LOG2;
|
|
case IIO_CHAN_INFO_OFFSET:
|
|
mutex_lock(&st->cfgs_lock);
|
|
if (st->channels[chan->address].cfg.bipolar)
|
|
*val = -(1 << (chan->scan_type.realbits - 1));
|
|
else
|
|
*val = 0;
|
|
|
|
mutex_unlock(&st->cfgs_lock);
|
|
return IIO_VAL_INT;
|
|
case IIO_CHAN_INFO_SAMP_FREQ:
|
|
mutex_lock(&st->cfgs_lock);
|
|
*val = st->channels[chan->address].cfg.odr;
|
|
mutex_unlock(&st->cfgs_lock);
|
|
|
|
return IIO_VAL_INT;
|
|
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
|
|
mutex_lock(&st->cfgs_lock);
|
|
*val = ad7124_get_3db_filter_freq(st, chan->scan_index);
|
|
mutex_unlock(&st->cfgs_lock);
|
|
|
|
return IIO_VAL_INT;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int ad7124_write_raw(struct iio_dev *indio_dev,
|
|
struct iio_chan_spec const *chan,
|
|
int val, int val2, long info)
|
|
{
|
|
struct ad7124_state *st = iio_priv(indio_dev);
|
|
unsigned int res, gain, full_scale, vref;
|
|
int ret = 0;
|
|
|
|
mutex_lock(&st->cfgs_lock);
|
|
|
|
switch (info) {
|
|
case IIO_CHAN_INFO_SAMP_FREQ:
|
|
if (val2 != 0) {
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
ad7124_set_channel_odr(st, chan->address, val);
|
|
break;
|
|
case IIO_CHAN_INFO_SCALE:
|
|
if (val != 0) {
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
if (st->channels[chan->address].cfg.bipolar)
|
|
full_scale = 1 << (chan->scan_type.realbits - 1);
|
|
else
|
|
full_scale = 1 << chan->scan_type.realbits;
|
|
|
|
vref = st->channels[chan->address].cfg.vref_mv * 1000000LL;
|
|
res = DIV_ROUND_CLOSEST(vref, full_scale);
|
|
gain = DIV_ROUND_CLOSEST(res, val2);
|
|
res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain);
|
|
|
|
if (st->channels[chan->address].cfg.pga_bits != res)
|
|
st->channels[chan->address].cfg.live = false;
|
|
|
|
st->channels[chan->address].cfg.pga_bits = res;
|
|
break;
|
|
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
|
|
if (val2 != 0) {
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
ad7124_set_3db_filter_freq(st, chan->address, val);
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
mutex_unlock(&st->cfgs_lock);
|
|
return ret;
|
|
}
|
|
|
|
static int ad7124_reg_access(struct iio_dev *indio_dev,
|
|
unsigned int reg,
|
|
unsigned int writeval,
|
|
unsigned int *readval)
|
|
{
|
|
struct ad7124_state *st = iio_priv(indio_dev);
|
|
int ret;
|
|
|
|
if (reg >= ARRAY_SIZE(ad7124_reg_size))
|
|
return -EINVAL;
|
|
|
|
if (readval)
|
|
ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
|
|
readval);
|
|
else
|
|
ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
|
|
writeval);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static IIO_CONST_ATTR(in_voltage_scale_available,
|
|
"0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
|
|
|
|
static struct attribute *ad7124_attributes[] = {
|
|
&iio_const_attr_in_voltage_scale_available.dev_attr.attr,
|
|
NULL,
|
|
};
|
|
|
|
static const struct attribute_group ad7124_attrs_group = {
|
|
.attrs = ad7124_attributes,
|
|
};
|
|
|
|
static const struct iio_info ad7124_info = {
|
|
.read_raw = ad7124_read_raw,
|
|
.write_raw = ad7124_write_raw,
|
|
.debugfs_reg_access = &ad7124_reg_access,
|
|
.validate_trigger = ad_sd_validate_trigger,
|
|
.attrs = &ad7124_attrs_group,
|
|
};
|
|
|
|
static int ad7124_soft_reset(struct ad7124_state *st)
|
|
{
|
|
unsigned int readval, timeout;
|
|
int ret;
|
|
|
|
ret = ad_sd_reset(&st->sd, 64);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
timeout = 100;
|
|
do {
|
|
ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
|
|
return 0;
|
|
|
|
/* The AD7124 requires typically 2ms to power up and settle */
|
|
usleep_range(100, 2000);
|
|
} while (--timeout);
|
|
|
|
dev_err(&st->sd.spi->dev, "Soft reset failed\n");
|
|
|
|
return -EIO;
|
|
}
|
|
|
|
static int ad7124_check_chip_id(struct ad7124_state *st)
|
|
{
|
|
unsigned int readval, chip_id, silicon_rev;
|
|
int ret;
|
|
|
|
ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
chip_id = AD7124_DEVICE_ID_GET(readval);
|
|
silicon_rev = AD7124_SILICON_REV_GET(readval);
|
|
|
|
if (chip_id != st->chip_info->chip_id) {
|
|
dev_err(&st->sd.spi->dev,
|
|
"Chip ID mismatch: expected %u, got %u\n",
|
|
st->chip_info->chip_id, chip_id);
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (silicon_rev == 0) {
|
|
dev_err(&st->sd.spi->dev,
|
|
"Silicon revision empty. Chip may not be present\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
|
|
struct device_node *np)
|
|
{
|
|
struct ad7124_state *st = iio_priv(indio_dev);
|
|
struct ad7124_channel_config *cfg;
|
|
struct ad7124_channel *channels;
|
|
struct device_node *child;
|
|
struct iio_chan_spec *chan;
|
|
unsigned int ain[2], channel = 0, tmp;
|
|
int ret;
|
|
|
|
st->num_channels = of_get_available_child_count(np);
|
|
if (!st->num_channels) {
|
|
dev_err(indio_dev->dev.parent, "no channel children\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
|
|
sizeof(*chan), GFP_KERNEL);
|
|
if (!chan)
|
|
return -ENOMEM;
|
|
|
|
channels = devm_kcalloc(indio_dev->dev.parent, st->num_channels, sizeof(*channels),
|
|
GFP_KERNEL);
|
|
if (!channels)
|
|
return -ENOMEM;
|
|
|
|
indio_dev->channels = chan;
|
|
indio_dev->num_channels = st->num_channels;
|
|
st->channels = channels;
|
|
|
|
for_each_available_child_of_node(np, child) {
|
|
cfg = &st->channels[channel].cfg;
|
|
|
|
ret = of_property_read_u32(child, "reg", &channel);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = of_property_read_u32_array(child, "diff-channels",
|
|
ain, 2);
|
|
if (ret)
|
|
goto err;
|
|
|
|
st->channels[channel].nr = channel;
|
|
st->channels[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
|
|
AD7124_CHANNEL_AINM(ain[1]);
|
|
|
|
cfg->bipolar = of_property_read_bool(child, "bipolar");
|
|
|
|
ret = of_property_read_u32(child, "adi,reference-select", &tmp);
|
|
if (ret)
|
|
cfg->refsel = AD7124_INT_REF;
|
|
else
|
|
cfg->refsel = tmp;
|
|
|
|
cfg->buf_positive = of_property_read_bool(child, "adi,buffered-positive");
|
|
cfg->buf_negative = of_property_read_bool(child, "adi,buffered-negative");
|
|
|
|
chan[channel] = ad7124_channel_template;
|
|
chan[channel].address = channel;
|
|
chan[channel].scan_index = channel;
|
|
chan[channel].channel = ain[0];
|
|
chan[channel].channel2 = ain[1];
|
|
}
|
|
|
|
return 0;
|
|
err:
|
|
of_node_put(child);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ad7124_setup(struct ad7124_state *st)
|
|
{
|
|
unsigned int fclk, power_mode;
|
|
int i, ret;
|
|
|
|
fclk = clk_get_rate(st->mclk);
|
|
if (!fclk)
|
|
return -EINVAL;
|
|
|
|
/* The power mode changes the master clock frequency */
|
|
power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
|
|
ARRAY_SIZE(ad7124_master_clk_freq_hz),
|
|
fclk);
|
|
if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
|
|
ret = clk_set_rate(st->mclk, fclk);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/* Set the power mode */
|
|
st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
|
|
st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
|
|
ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
mutex_init(&st->cfgs_lock);
|
|
INIT_KFIFO(st->live_cfgs_fifo);
|
|
for (i = 0; i < st->num_channels; i++) {
|
|
|
|
ret = ad7124_init_config_vref(st, &st->channels[i].cfg);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/*
|
|
* 9.38 SPS is the minimum output data rate supported
|
|
* regardless of the selected power mode. Round it up to 10 and
|
|
* set all channels to this default value.
|
|
*/
|
|
ad7124_set_channel_odr(st, i, 10);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ad7124_probe(struct spi_device *spi)
|
|
{
|
|
const struct ad7124_chip_info *info;
|
|
struct ad7124_state *st;
|
|
struct iio_dev *indio_dev;
|
|
int i, ret;
|
|
|
|
info = of_device_get_match_data(&spi->dev);
|
|
if (!info)
|
|
return -ENODEV;
|
|
|
|
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
|
|
if (!indio_dev)
|
|
return -ENOMEM;
|
|
|
|
st = iio_priv(indio_dev);
|
|
|
|
st->chip_info = info;
|
|
|
|
ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
|
|
|
|
spi_set_drvdata(spi, indio_dev);
|
|
|
|
indio_dev->name = st->chip_info->name;
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
indio_dev->info = &ad7124_info;
|
|
|
|
ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
|
|
if (i == AD7124_INT_REF)
|
|
continue;
|
|
|
|
st->vref[i] = devm_regulator_get_optional(&spi->dev,
|
|
ad7124_ref_names[i]);
|
|
if (PTR_ERR(st->vref[i]) == -ENODEV)
|
|
continue;
|
|
else if (IS_ERR(st->vref[i]))
|
|
return PTR_ERR(st->vref[i]);
|
|
|
|
ret = regulator_enable(st->vref[i]);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
st->mclk = devm_clk_get(&spi->dev, "mclk");
|
|
if (IS_ERR(st->mclk)) {
|
|
ret = PTR_ERR(st->mclk);
|
|
goto error_regulator_disable;
|
|
}
|
|
|
|
ret = clk_prepare_enable(st->mclk);
|
|
if (ret < 0)
|
|
goto error_regulator_disable;
|
|
|
|
ret = ad7124_soft_reset(st);
|
|
if (ret < 0)
|
|
goto error_clk_disable_unprepare;
|
|
|
|
ret = ad7124_check_chip_id(st);
|
|
if (ret)
|
|
goto error_clk_disable_unprepare;
|
|
|
|
ret = ad7124_setup(st);
|
|
if (ret < 0)
|
|
goto error_clk_disable_unprepare;
|
|
|
|
ret = ad_sd_setup_buffer_and_trigger(indio_dev);
|
|
if (ret < 0)
|
|
goto error_clk_disable_unprepare;
|
|
|
|
ret = iio_device_register(indio_dev);
|
|
if (ret < 0) {
|
|
dev_err(&spi->dev, "Failed to register iio device\n");
|
|
goto error_remove_trigger;
|
|
}
|
|
|
|
return 0;
|
|
|
|
error_remove_trigger:
|
|
ad_sd_cleanup_buffer_and_trigger(indio_dev);
|
|
error_clk_disable_unprepare:
|
|
clk_disable_unprepare(st->mclk);
|
|
error_regulator_disable:
|
|
for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
|
|
if (!IS_ERR_OR_NULL(st->vref[i]))
|
|
regulator_disable(st->vref[i]);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ad7124_remove(struct spi_device *spi)
|
|
{
|
|
struct iio_dev *indio_dev = spi_get_drvdata(spi);
|
|
struct ad7124_state *st = iio_priv(indio_dev);
|
|
int i;
|
|
|
|
iio_device_unregister(indio_dev);
|
|
ad_sd_cleanup_buffer_and_trigger(indio_dev);
|
|
clk_disable_unprepare(st->mclk);
|
|
|
|
for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
|
|
if (!IS_ERR_OR_NULL(st->vref[i]))
|
|
regulator_disable(st->vref[i]);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id ad7124_of_match[] = {
|
|
{ .compatible = "adi,ad7124-4",
|
|
.data = &ad7124_chip_info_tbl[ID_AD7124_4], },
|
|
{ .compatible = "adi,ad7124-8",
|
|
.data = &ad7124_chip_info_tbl[ID_AD7124_8], },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ad7124_of_match);
|
|
|
|
static struct spi_driver ad71124_driver = {
|
|
.driver = {
|
|
.name = "ad7124",
|
|
.of_match_table = ad7124_of_match,
|
|
},
|
|
.probe = ad7124_probe,
|
|
.remove = ad7124_remove,
|
|
};
|
|
module_spi_driver(ad71124_driver);
|
|
|
|
MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
|
|
MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
|
|
MODULE_LICENSE("GPL");
|