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![Xu Wang](/assets/img/avatar_default.png)
Because clk_prepare_enable() and clk_disable_unprepare() already checked NULL clock parameter, so the additional checks are unnecessary, just remove them. Signed-off-by: Xu Wang <vulab@iscas.ac.cn> Acked-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20201218093512.871-1-vulab@iscas.ac.cn Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
846 lines
22 KiB
C
846 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* This file is part of STM32 ADC driver
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*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
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* Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
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*
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* Inspired from: fsl-imx25-tsadc
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*
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdesc.h>
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#include <linux/irqdomain.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include "stm32-adc-core.h"
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#define STM32_ADC_CORE_SLEEP_DELAY_MS 2000
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/* SYSCFG registers */
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#define STM32MP1_SYSCFG_PMCSETR 0x04
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#define STM32MP1_SYSCFG_PMCCLRR 0x44
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/* SYSCFG bit fields */
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#define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9)
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/* SYSCFG capability flags */
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#define HAS_VBOOSTER BIT(0)
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#define HAS_ANASWVDD BIT(1)
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/**
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* struct stm32_adc_common_regs - stm32 common registers
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* @csr: common status register offset
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* @ccr: common control register offset
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* @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n
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* @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n
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* @ier: interrupt enable register offset for each adc
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* @eocie_msk: end of conversion interrupt enable mask in @ier
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*/
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struct stm32_adc_common_regs {
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u32 csr;
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u32 ccr;
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u32 eoc_msk[STM32_ADC_MAX_ADCS];
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u32 ovr_msk[STM32_ADC_MAX_ADCS];
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u32 ier;
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u32 eocie_msk;
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};
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struct stm32_adc_priv;
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/**
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* struct stm32_adc_priv_cfg - stm32 core compatible configuration data
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* @regs: common registers for all instances
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* @clk_sel: clock selection routine
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* @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
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* @has_syscfg: SYSCFG capability flags
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* @num_irqs: number of interrupt lines
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*/
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struct stm32_adc_priv_cfg {
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const struct stm32_adc_common_regs *regs;
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int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
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u32 max_clk_rate_hz;
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unsigned int has_syscfg;
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unsigned int num_irqs;
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};
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/**
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* struct stm32_adc_priv - stm32 ADC core private data
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* @irq: irq(s) for ADC block
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* @domain: irq domain reference
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* @aclk: clock reference for the analog circuitry
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* @bclk: bus clock common for all ADCs, depends on part used
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* @max_clk_rate: desired maximum clock rate
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* @booster: booster supply reference
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* @vdd: vdd supply reference
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* @vdda: vdda analog supply reference
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* @vref: regulator reference
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* @vdd_uv: vdd supply voltage (microvolts)
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* @vdda_uv: vdda supply voltage (microvolts)
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* @cfg: compatible configuration data
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* @common: common data for all ADC instances
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* @ccr_bak: backup CCR in low power mode
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* @syscfg: reference to syscon, system control registers
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*/
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struct stm32_adc_priv {
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int irq[STM32_ADC_MAX_ADCS];
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struct irq_domain *domain;
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struct clk *aclk;
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struct clk *bclk;
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u32 max_clk_rate;
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struct regulator *booster;
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struct regulator *vdd;
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struct regulator *vdda;
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struct regulator *vref;
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int vdd_uv;
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int vdda_uv;
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const struct stm32_adc_priv_cfg *cfg;
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struct stm32_adc_common common;
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u32 ccr_bak;
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struct regmap *syscfg;
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};
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static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
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{
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return container_of(com, struct stm32_adc_priv, common);
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}
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/* STM32F4 ADC internal common clock prescaler division ratios */
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static int stm32f4_pclk_div[] = {2, 4, 6, 8};
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/**
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* stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
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* @pdev: platform device
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* @priv: stm32 ADC core private data
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* Select clock prescaler used for analog conversions, before using ADC.
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*/
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static int stm32f4_adc_clk_sel(struct platform_device *pdev,
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struct stm32_adc_priv *priv)
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{
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unsigned long rate;
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u32 val;
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int i;
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/* stm32f4 has one clk input for analog (mandatory), enforce it here */
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if (!priv->aclk) {
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dev_err(&pdev->dev, "No 'adc' clock found\n");
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return -ENOENT;
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}
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rate = clk_get_rate(priv->aclk);
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if (!rate) {
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dev_err(&pdev->dev, "Invalid clock rate: 0\n");
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return -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
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if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate)
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break;
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}
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if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
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dev_err(&pdev->dev, "adc clk selection failed\n");
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return -EINVAL;
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}
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priv->common.rate = rate / stm32f4_pclk_div[i];
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val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
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val &= ~STM32F4_ADC_ADCPRE_MASK;
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val |= i << STM32F4_ADC_ADCPRE_SHIFT;
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writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
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dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
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priv->common.rate / 1000);
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return 0;
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}
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/**
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* struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
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* @ckmode: ADC clock mode, Async or sync with prescaler.
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* @presc: prescaler bitfield for async clock mode
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* @div: prescaler division ratio
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*/
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struct stm32h7_adc_ck_spec {
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u32 ckmode;
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u32 presc;
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int div;
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};
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static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
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/* 00: CK_ADC[1..3]: Asynchronous clock modes */
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{ 0, 0, 1 },
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{ 0, 1, 2 },
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{ 0, 2, 4 },
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{ 0, 3, 6 },
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{ 0, 4, 8 },
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{ 0, 5, 10 },
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{ 0, 6, 12 },
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{ 0, 7, 16 },
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{ 0, 8, 32 },
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{ 0, 9, 64 },
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{ 0, 10, 128 },
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{ 0, 11, 256 },
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/* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
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{ 1, 0, 1 },
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{ 2, 0, 2 },
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{ 3, 0, 4 },
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};
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static int stm32h7_adc_clk_sel(struct platform_device *pdev,
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struct stm32_adc_priv *priv)
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{
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u32 ckmode, presc, val;
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unsigned long rate;
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int i, div, duty;
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/* stm32h7 bus clock is common for all ADC instances (mandatory) */
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if (!priv->bclk) {
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dev_err(&pdev->dev, "No 'bus' clock found\n");
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return -ENOENT;
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}
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/*
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* stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
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* So, choice is to have bus clock mandatory and adc clock optional.
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* If optional 'adc' clock has been found, then try to use it first.
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*/
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if (priv->aclk) {
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/*
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* Asynchronous clock modes (e.g. ckmode == 0)
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* From spec: PLL output musn't exceed max rate
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*/
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rate = clk_get_rate(priv->aclk);
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if (!rate) {
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dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
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return -EINVAL;
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}
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/* If duty is an error, kindly use at least /2 divider */
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duty = clk_get_scaled_duty_cycle(priv->aclk, 100);
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if (duty < 0)
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dev_warn(&pdev->dev, "adc clock duty: %d\n", duty);
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for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
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ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
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presc = stm32h7_adc_ckmodes_spec[i].presc;
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div = stm32h7_adc_ckmodes_spec[i].div;
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if (ckmode)
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continue;
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/*
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* For proper operation, clock duty cycle range is 49%
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* to 51%. Apply at least /2 prescaler otherwise.
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*/
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if (div == 1 && (duty < 49 || duty > 51))
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continue;
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if ((rate / div) <= priv->max_clk_rate)
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goto out;
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}
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}
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/* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
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rate = clk_get_rate(priv->bclk);
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if (!rate) {
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dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
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return -EINVAL;
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}
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duty = clk_get_scaled_duty_cycle(priv->bclk, 100);
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if (duty < 0)
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dev_warn(&pdev->dev, "bus clock duty: %d\n", duty);
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for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
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ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
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presc = stm32h7_adc_ckmodes_spec[i].presc;
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div = stm32h7_adc_ckmodes_spec[i].div;
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if (!ckmode)
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continue;
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if (div == 1 && (duty < 49 || duty > 51))
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continue;
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if ((rate / div) <= priv->max_clk_rate)
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goto out;
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}
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dev_err(&pdev->dev, "adc clk selection failed\n");
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return -EINVAL;
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out:
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/* rate used later by each ADC instance to control BOOST mode */
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priv->common.rate = rate / div;
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/* Set common clock mode and prescaler */
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val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
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val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
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val |= ckmode << STM32H7_CKMODE_SHIFT;
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val |= presc << STM32H7_PRESC_SHIFT;
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writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
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dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
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ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
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return 0;
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}
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/* STM32F4 common registers definitions */
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static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
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.csr = STM32F4_ADC_CSR,
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.ccr = STM32F4_ADC_CCR,
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.eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3},
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.ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3},
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.ier = STM32F4_ADC_CR1,
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.eocie_msk = STM32F4_EOCIE,
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};
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/* STM32H7 common registers definitions */
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static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
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.csr = STM32H7_ADC_CSR,
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.ccr = STM32H7_ADC_CCR,
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.eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV},
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.ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV},
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.ier = STM32H7_ADC_IER,
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.eocie_msk = STM32H7_EOCIE,
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};
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static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
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0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2,
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};
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static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv,
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unsigned int adc)
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{
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u32 ier, offset = stm32_adc_offset[adc];
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ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier);
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return ier & priv->cfg->regs->eocie_msk;
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}
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/* ADC common interrupt for all instances */
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static void stm32_adc_irq_handler(struct irq_desc *desc)
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{
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struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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int i;
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u32 status;
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chained_irq_enter(chip, desc);
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status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
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/*
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* End of conversion may be handled by using IRQ or DMA. There may be a
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* race here when two conversions complete at the same time on several
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* ADCs. EOC may be read 'set' for several ADCs, with:
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* - an ADC configured to use DMA (EOC triggers the DMA request, and
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* is then automatically cleared by DR read in hardware)
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* - an ADC configured to use IRQs (EOCIE bit is set. The handler must
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* be called in this case)
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* So both EOC status bit in CSR and EOCIE control bit must be checked
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* before invoking the interrupt handler (e.g. call ISR only for
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* IRQ-enabled ADCs).
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*/
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for (i = 0; i < priv->cfg->num_irqs; i++) {
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if ((status & priv->cfg->regs->eoc_msk[i] &&
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stm32_adc_eoc_enabled(priv, i)) ||
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(status & priv->cfg->regs->ovr_msk[i]))
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generic_handle_irq(irq_find_mapping(priv->domain, i));
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}
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chained_irq_exit(chip, desc);
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};
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static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_data(irq, d->host_data);
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irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
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return 0;
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}
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static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
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{
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irq_set_chip_and_handler(irq, NULL, NULL);
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irq_set_chip_data(irq, NULL);
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}
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static const struct irq_domain_ops stm32_adc_domain_ops = {
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.map = stm32_adc_domain_map,
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.unmap = stm32_adc_domain_unmap,
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.xlate = irq_domain_xlate_onecell,
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};
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static int stm32_adc_irq_probe(struct platform_device *pdev,
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struct stm32_adc_priv *priv)
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{
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struct device_node *np = pdev->dev.of_node;
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unsigned int i;
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/*
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* Interrupt(s) must be provided, depending on the compatible:
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* - stm32f4/h7 shares a common interrupt line.
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* - stm32mp1, has one line per ADC
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*/
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for (i = 0; i < priv->cfg->num_irqs; i++) {
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priv->irq[i] = platform_get_irq(pdev, i);
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if (priv->irq[i] < 0)
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return priv->irq[i];
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}
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priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
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&stm32_adc_domain_ops,
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priv);
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if (!priv->domain) {
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dev_err(&pdev->dev, "Failed to add irq domain\n");
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return -ENOMEM;
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}
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for (i = 0; i < priv->cfg->num_irqs; i++) {
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irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
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irq_set_handler_data(priv->irq[i], priv);
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}
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return 0;
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}
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static void stm32_adc_irq_remove(struct platform_device *pdev,
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struct stm32_adc_priv *priv)
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{
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int hwirq;
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unsigned int i;
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for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
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irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
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irq_domain_remove(priv->domain);
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for (i = 0; i < priv->cfg->num_irqs; i++)
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irq_set_chained_handler(priv->irq[i], NULL);
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}
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static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv,
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struct device *dev)
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{
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int ret;
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/*
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* On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog
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* switches (via PCSEL) which have reduced performances when their
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* supply is below 2.7V (vdda by default):
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* - Voltage booster can be used, to get full ADC performances
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* (increases power consumption).
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* - Vdd can be used to supply them, if above 2.7V (STM32MP1 only).
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*
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* Recommended settings for ANASWVDD and EN_BOOSTER:
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* - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1)
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* - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1
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* - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default)
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*/
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if (priv->vdda_uv < 2700000) {
|
|
if (priv->syscfg && priv->vdd_uv > 2700000) {
|
|
ret = regulator_enable(priv->vdd);
|
|
if (ret < 0) {
|
|
dev_err(dev, "vdd enable failed %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = regmap_write(priv->syscfg,
|
|
STM32MP1_SYSCFG_PMCSETR,
|
|
STM32MP1_SYSCFG_ANASWVDD_MASK);
|
|
if (ret < 0) {
|
|
regulator_disable(priv->vdd);
|
|
dev_err(dev, "vdd select failed, %d\n", ret);
|
|
return ret;
|
|
}
|
|
dev_dbg(dev, "analog switches supplied by vdd\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
if (priv->booster) {
|
|
/*
|
|
* This is optional, as this is a trade-off between
|
|
* analog performance and power consumption.
|
|
*/
|
|
ret = regulator_enable(priv->booster);
|
|
if (ret < 0) {
|
|
dev_err(dev, "booster enable failed %d\n", ret);
|
|
return ret;
|
|
}
|
|
dev_dbg(dev, "analog switches supplied by booster\n");
|
|
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/* Fallback using vdda (default), nothing to do */
|
|
dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n",
|
|
priv->vdda_uv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv)
|
|
{
|
|
if (priv->vdda_uv < 2700000) {
|
|
if (priv->syscfg && priv->vdd_uv > 2700000) {
|
|
regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR,
|
|
STM32MP1_SYSCFG_ANASWVDD_MASK);
|
|
regulator_disable(priv->vdd);
|
|
return;
|
|
}
|
|
if (priv->booster)
|
|
regulator_disable(priv->booster);
|
|
}
|
|
}
|
|
|
|
static int stm32_adc_core_hw_start(struct device *dev)
|
|
{
|
|
struct stm32_adc_common *common = dev_get_drvdata(dev);
|
|
struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
|
|
int ret;
|
|
|
|
ret = regulator_enable(priv->vdda);
|
|
if (ret < 0) {
|
|
dev_err(dev, "vdda enable failed %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = regulator_get_voltage(priv->vdda);
|
|
if (ret < 0) {
|
|
dev_err(dev, "vdda get voltage failed, %d\n", ret);
|
|
goto err_vdda_disable;
|
|
}
|
|
priv->vdda_uv = ret;
|
|
|
|
ret = stm32_adc_core_switches_supply_en(priv, dev);
|
|
if (ret < 0)
|
|
goto err_vdda_disable;
|
|
|
|
ret = regulator_enable(priv->vref);
|
|
if (ret < 0) {
|
|
dev_err(dev, "vref enable failed\n");
|
|
goto err_switches_dis;
|
|
}
|
|
|
|
ret = clk_prepare_enable(priv->bclk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "bus clk enable failed\n");
|
|
goto err_regulator_disable;
|
|
}
|
|
|
|
ret = clk_prepare_enable(priv->aclk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "adc clk enable failed\n");
|
|
goto err_bclk_disable;
|
|
}
|
|
|
|
writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr);
|
|
|
|
return 0;
|
|
|
|
err_bclk_disable:
|
|
clk_disable_unprepare(priv->bclk);
|
|
err_regulator_disable:
|
|
regulator_disable(priv->vref);
|
|
err_switches_dis:
|
|
stm32_adc_core_switches_supply_dis(priv);
|
|
err_vdda_disable:
|
|
regulator_disable(priv->vdda);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void stm32_adc_core_hw_stop(struct device *dev)
|
|
{
|
|
struct stm32_adc_common *common = dev_get_drvdata(dev);
|
|
struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
|
|
|
|
/* Backup CCR that may be lost (depends on power state to achieve) */
|
|
priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr);
|
|
clk_disable_unprepare(priv->aclk);
|
|
clk_disable_unprepare(priv->bclk);
|
|
regulator_disable(priv->vref);
|
|
stm32_adc_core_switches_supply_dis(priv);
|
|
regulator_disable(priv->vdda);
|
|
}
|
|
|
|
static int stm32_adc_core_switches_probe(struct device *dev,
|
|
struct stm32_adc_priv *priv)
|
|
{
|
|
struct device_node *np = dev->of_node;
|
|
int ret;
|
|
|
|
/* Analog switches supply can be controlled by syscfg (optional) */
|
|
priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
|
|
if (IS_ERR(priv->syscfg)) {
|
|
ret = PTR_ERR(priv->syscfg);
|
|
if (ret != -ENODEV)
|
|
return dev_err_probe(dev, ret, "Can't probe syscfg\n");
|
|
|
|
priv->syscfg = NULL;
|
|
}
|
|
|
|
/* Booster can be used to supply analog switches (optional) */
|
|
if (priv->cfg->has_syscfg & HAS_VBOOSTER &&
|
|
of_property_read_bool(np, "booster-supply")) {
|
|
priv->booster = devm_regulator_get_optional(dev, "booster");
|
|
if (IS_ERR(priv->booster)) {
|
|
ret = PTR_ERR(priv->booster);
|
|
if (ret != -ENODEV)
|
|
return dev_err_probe(dev, ret, "can't get booster\n");
|
|
|
|
priv->booster = NULL;
|
|
}
|
|
}
|
|
|
|
/* Vdd can be used to supply analog switches (optional) */
|
|
if (priv->cfg->has_syscfg & HAS_ANASWVDD &&
|
|
of_property_read_bool(np, "vdd-supply")) {
|
|
priv->vdd = devm_regulator_get_optional(dev, "vdd");
|
|
if (IS_ERR(priv->vdd)) {
|
|
ret = PTR_ERR(priv->vdd);
|
|
if (ret != -ENODEV)
|
|
return dev_err_probe(dev, ret, "can't get vdd\n");
|
|
|
|
priv->vdd = NULL;
|
|
}
|
|
}
|
|
|
|
if (priv->vdd) {
|
|
ret = regulator_enable(priv->vdd);
|
|
if (ret < 0) {
|
|
dev_err(dev, "vdd enable failed %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = regulator_get_voltage(priv->vdd);
|
|
if (ret < 0) {
|
|
dev_err(dev, "vdd get voltage failed %d\n", ret);
|
|
regulator_disable(priv->vdd);
|
|
return ret;
|
|
}
|
|
priv->vdd_uv = ret;
|
|
|
|
regulator_disable(priv->vdd);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_adc_probe(struct platform_device *pdev)
|
|
{
|
|
struct stm32_adc_priv *priv;
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct resource *res;
|
|
u32 max_rate;
|
|
int ret;
|
|
|
|
if (!pdev->dev.of_node)
|
|
return -ENODEV;
|
|
|
|
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
platform_set_drvdata(pdev, &priv->common);
|
|
|
|
priv->cfg = (const struct stm32_adc_priv_cfg *)
|
|
of_match_device(dev->driver->of_match_table, dev)->data;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
priv->common.base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(priv->common.base))
|
|
return PTR_ERR(priv->common.base);
|
|
priv->common.phys_base = res->start;
|
|
|
|
priv->vdda = devm_regulator_get(&pdev->dev, "vdda");
|
|
if (IS_ERR(priv->vdda))
|
|
return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda),
|
|
"vdda get failed\n");
|
|
|
|
priv->vref = devm_regulator_get(&pdev->dev, "vref");
|
|
if (IS_ERR(priv->vref))
|
|
return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref),
|
|
"vref get failed\n");
|
|
|
|
priv->aclk = devm_clk_get_optional(&pdev->dev, "adc");
|
|
if (IS_ERR(priv->aclk))
|
|
return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk),
|
|
"Can't get 'adc' clock\n");
|
|
|
|
priv->bclk = devm_clk_get_optional(&pdev->dev, "bus");
|
|
if (IS_ERR(priv->bclk))
|
|
return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk),
|
|
"Can't get 'bus' clock\n");
|
|
|
|
ret = stm32_adc_core_switches_probe(dev, priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pm_runtime_get_noresume(dev);
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS);
|
|
pm_runtime_use_autosuspend(dev);
|
|
pm_runtime_enable(dev);
|
|
|
|
ret = stm32_adc_core_hw_start(dev);
|
|
if (ret)
|
|
goto err_pm_stop;
|
|
|
|
ret = regulator_get_voltage(priv->vref);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
|
|
goto err_hw_stop;
|
|
}
|
|
priv->common.vref_mv = ret / 1000;
|
|
dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
|
|
|
|
ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz",
|
|
&max_rate);
|
|
if (!ret)
|
|
priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz);
|
|
else
|
|
priv->max_clk_rate = priv->cfg->max_clk_rate_hz;
|
|
|
|
ret = priv->cfg->clk_sel(pdev, priv);
|
|
if (ret < 0)
|
|
goto err_hw_stop;
|
|
|
|
ret = stm32_adc_irq_probe(pdev, priv);
|
|
if (ret < 0)
|
|
goto err_hw_stop;
|
|
|
|
ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "failed to populate DT children\n");
|
|
goto err_irq_remove;
|
|
}
|
|
|
|
pm_runtime_mark_last_busy(dev);
|
|
pm_runtime_put_autosuspend(dev);
|
|
|
|
return 0;
|
|
|
|
err_irq_remove:
|
|
stm32_adc_irq_remove(pdev, priv);
|
|
err_hw_stop:
|
|
stm32_adc_core_hw_stop(dev);
|
|
err_pm_stop:
|
|
pm_runtime_disable(dev);
|
|
pm_runtime_set_suspended(dev);
|
|
pm_runtime_put_noidle(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int stm32_adc_remove(struct platform_device *pdev)
|
|
{
|
|
struct stm32_adc_common *common = platform_get_drvdata(pdev);
|
|
struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
|
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
of_platform_depopulate(&pdev->dev);
|
|
stm32_adc_irq_remove(pdev, priv);
|
|
stm32_adc_core_hw_stop(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_set_suspended(&pdev->dev);
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_PM)
|
|
static int stm32_adc_core_runtime_suspend(struct device *dev)
|
|
{
|
|
stm32_adc_core_hw_stop(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_adc_core_runtime_resume(struct device *dev)
|
|
{
|
|
return stm32_adc_core_hw_start(dev);
|
|
}
|
|
|
|
static int stm32_adc_core_runtime_idle(struct device *dev)
|
|
{
|
|
pm_runtime_mark_last_busy(dev);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops stm32_adc_core_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend,
|
|
stm32_adc_core_runtime_resume,
|
|
stm32_adc_core_runtime_idle)
|
|
};
|
|
|
|
static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
|
|
.regs = &stm32f4_adc_common_regs,
|
|
.clk_sel = stm32f4_adc_clk_sel,
|
|
.max_clk_rate_hz = 36000000,
|
|
.num_irqs = 1,
|
|
};
|
|
|
|
static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
|
|
.regs = &stm32h7_adc_common_regs,
|
|
.clk_sel = stm32h7_adc_clk_sel,
|
|
.max_clk_rate_hz = 36000000,
|
|
.has_syscfg = HAS_VBOOSTER,
|
|
.num_irqs = 1,
|
|
};
|
|
|
|
static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
|
|
.regs = &stm32h7_adc_common_regs,
|
|
.clk_sel = stm32h7_adc_clk_sel,
|
|
.max_clk_rate_hz = 40000000,
|
|
.has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD,
|
|
.num_irqs = 2,
|
|
};
|
|
|
|
static const struct of_device_id stm32_adc_of_match[] = {
|
|
{
|
|
.compatible = "st,stm32f4-adc-core",
|
|
.data = (void *)&stm32f4_adc_priv_cfg
|
|
}, {
|
|
.compatible = "st,stm32h7-adc-core",
|
|
.data = (void *)&stm32h7_adc_priv_cfg
|
|
}, {
|
|
.compatible = "st,stm32mp1-adc-core",
|
|
.data = (void *)&stm32mp1_adc_priv_cfg
|
|
}, {
|
|
},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
|
|
|
|
static struct platform_driver stm32_adc_driver = {
|
|
.probe = stm32_adc_probe,
|
|
.remove = stm32_adc_remove,
|
|
.driver = {
|
|
.name = "stm32-adc-core",
|
|
.of_match_table = stm32_adc_of_match,
|
|
.pm = &stm32_adc_core_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(stm32_adc_driver);
|
|
|
|
MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
|
|
MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:stm32-adc-core");
|