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![Xu Wang](/assets/img/avatar_default.png)
ecause clk_disable_unprepare() already checked NULL clock parameter, so the additional check is unnecessary, just remove it. Signed-off-by: Xu Wang <vulab@iscas.ac.cn> Link: https://lore.kernel.org/r/20201231085322.24398-1-vulab@iscas.ac.cn Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
457 lines
11 KiB
C
457 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* This file is part the core part STM32 DFSDM driver
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*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com> for STMicroelectronics.
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*/
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#include <linux/clk.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include "stm32-dfsdm.h"
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struct stm32_dfsdm_dev_data {
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unsigned int num_filters;
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unsigned int num_channels;
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const struct regmap_config *regmap_cfg;
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};
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#define STM32H7_DFSDM_NUM_FILTERS 4
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#define STM32H7_DFSDM_NUM_CHANNELS 8
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#define STM32MP1_DFSDM_NUM_FILTERS 6
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#define STM32MP1_DFSDM_NUM_CHANNELS 8
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static bool stm32_dfsdm_volatile_reg(struct device *dev, unsigned int reg)
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{
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if (reg < DFSDM_FILTER_BASE_ADR)
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return false;
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/*
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* Mask is done on register to avoid to list registers of all
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* filter instances.
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*/
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switch (reg & DFSDM_FILTER_REG_MASK) {
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case DFSDM_CR1(0) & DFSDM_FILTER_REG_MASK:
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case DFSDM_ISR(0) & DFSDM_FILTER_REG_MASK:
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case DFSDM_JDATAR(0) & DFSDM_FILTER_REG_MASK:
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case DFSDM_RDATAR(0) & DFSDM_FILTER_REG_MASK:
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return true;
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}
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return false;
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}
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static const struct regmap_config stm32h7_dfsdm_regmap_cfg = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = sizeof(u32),
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.max_register = 0x2B8,
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.volatile_reg = stm32_dfsdm_volatile_reg,
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.fast_io = true,
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};
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static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_data = {
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.num_filters = STM32H7_DFSDM_NUM_FILTERS,
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.num_channels = STM32H7_DFSDM_NUM_CHANNELS,
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.regmap_cfg = &stm32h7_dfsdm_regmap_cfg,
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};
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static const struct regmap_config stm32mp1_dfsdm_regmap_cfg = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = sizeof(u32),
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.max_register = 0x7fc,
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.volatile_reg = stm32_dfsdm_volatile_reg,
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.fast_io = true,
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};
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static const struct stm32_dfsdm_dev_data stm32mp1_dfsdm_data = {
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.num_filters = STM32MP1_DFSDM_NUM_FILTERS,
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.num_channels = STM32MP1_DFSDM_NUM_CHANNELS,
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.regmap_cfg = &stm32mp1_dfsdm_regmap_cfg,
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};
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struct dfsdm_priv {
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struct platform_device *pdev; /* platform device */
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struct stm32_dfsdm dfsdm; /* common data exported for all instances */
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unsigned int spi_clk_out_div; /* SPI clkout divider value */
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atomic_t n_active_ch; /* number of current active channels */
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struct clk *clk; /* DFSDM clock */
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struct clk *aclk; /* audio clock */
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};
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static inline struct dfsdm_priv *to_stm32_dfsdm_priv(struct stm32_dfsdm *dfsdm)
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{
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return container_of(dfsdm, struct dfsdm_priv, dfsdm);
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}
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static int stm32_dfsdm_clk_prepare_enable(struct stm32_dfsdm *dfsdm)
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{
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struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
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int ret;
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ret = clk_prepare_enable(priv->clk);
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if (ret || !priv->aclk)
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return ret;
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ret = clk_prepare_enable(priv->aclk);
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if (ret)
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clk_disable_unprepare(priv->clk);
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return ret;
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}
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static void stm32_dfsdm_clk_disable_unprepare(struct stm32_dfsdm *dfsdm)
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{
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struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
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clk_disable_unprepare(priv->aclk);
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clk_disable_unprepare(priv->clk);
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}
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/**
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* stm32_dfsdm_start_dfsdm - start global dfsdm interface.
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*
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* Enable interface if n_active_ch is not null.
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* @dfsdm: Handle used to retrieve dfsdm context.
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*/
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int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm)
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{
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struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
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struct device *dev = &priv->pdev->dev;
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unsigned int clk_div = priv->spi_clk_out_div, clk_src;
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int ret;
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if (atomic_inc_return(&priv->n_active_ch) == 1) {
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ret = pm_runtime_get_sync(dev);
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if (ret < 0) {
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pm_runtime_put_noidle(dev);
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goto error_ret;
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}
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/* select clock source, e.g. 0 for "dfsdm" or 1 for "audio" */
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clk_src = priv->aclk ? 1 : 0;
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ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
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DFSDM_CHCFGR1_CKOUTSRC_MASK,
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DFSDM_CHCFGR1_CKOUTSRC(clk_src));
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if (ret < 0)
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goto pm_put;
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/* Output the SPI CLKOUT (if clk_div == 0 clock if OFF) */
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ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
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DFSDM_CHCFGR1_CKOUTDIV_MASK,
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DFSDM_CHCFGR1_CKOUTDIV(clk_div));
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if (ret < 0)
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goto pm_put;
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/* Global enable of DFSDM interface */
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ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
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DFSDM_CHCFGR1_DFSDMEN_MASK,
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DFSDM_CHCFGR1_DFSDMEN(1));
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if (ret < 0)
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goto pm_put;
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}
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dev_dbg(dev, "%s: n_active_ch %d\n", __func__,
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atomic_read(&priv->n_active_ch));
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return 0;
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pm_put:
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pm_runtime_put_sync(dev);
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error_ret:
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atomic_dec(&priv->n_active_ch);
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return ret;
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}
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EXPORT_SYMBOL_GPL(stm32_dfsdm_start_dfsdm);
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/**
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* stm32_dfsdm_stop_dfsdm - stop global DFSDM interface.
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*
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* Disable interface if n_active_ch is null
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* @dfsdm: Handle used to retrieve dfsdm context.
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*/
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int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm)
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{
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struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
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int ret;
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if (atomic_dec_and_test(&priv->n_active_ch)) {
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/* Global disable of DFSDM interface */
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ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
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DFSDM_CHCFGR1_DFSDMEN_MASK,
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DFSDM_CHCFGR1_DFSDMEN(0));
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if (ret < 0)
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return ret;
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/* Stop SPI CLKOUT */
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ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
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DFSDM_CHCFGR1_CKOUTDIV_MASK,
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DFSDM_CHCFGR1_CKOUTDIV(0));
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if (ret < 0)
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return ret;
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pm_runtime_put_sync(&priv->pdev->dev);
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}
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dev_dbg(&priv->pdev->dev, "%s: n_active_ch %d\n", __func__,
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atomic_read(&priv->n_active_ch));
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return 0;
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}
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EXPORT_SYMBOL_GPL(stm32_dfsdm_stop_dfsdm);
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static int stm32_dfsdm_parse_of(struct platform_device *pdev,
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struct dfsdm_priv *priv)
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{
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struct device_node *node = pdev->dev.of_node;
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struct resource *res;
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unsigned long clk_freq, divider;
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unsigned int spi_freq, rem;
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int ret;
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if (!node)
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return -EINVAL;
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priv->dfsdm.base = devm_platform_get_and_ioremap_resource(pdev, 0,
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&res);
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if (IS_ERR(priv->dfsdm.base))
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return PTR_ERR(priv->dfsdm.base);
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priv->dfsdm.phys_base = res->start;
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/*
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* "dfsdm" clock is mandatory for DFSDM peripheral clocking.
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* "dfsdm" or "audio" clocks can be used as source clock for
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* the SPI clock out signal and internal processing, depending
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* on use case.
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*/
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priv->clk = devm_clk_get(&pdev->dev, "dfsdm");
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if (IS_ERR(priv->clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk),
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"Failed to get clock\n");
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priv->aclk = devm_clk_get(&pdev->dev, "audio");
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if (IS_ERR(priv->aclk))
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priv->aclk = NULL;
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if (priv->aclk)
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clk_freq = clk_get_rate(priv->aclk);
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else
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clk_freq = clk_get_rate(priv->clk);
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/* SPI clock out frequency */
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ret = of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
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&spi_freq);
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if (ret < 0) {
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/* No SPI master mode */
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return 0;
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}
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divider = div_u64_rem(clk_freq, spi_freq, &rem);
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/* Round up divider when ckout isn't precise, not to exceed spi_freq */
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if (rem)
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divider++;
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/* programmable divider is in range of [2:256] */
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if (divider < 2 || divider > 256) {
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dev_err(&pdev->dev, "spi-max-frequency not achievable\n");
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return -EINVAL;
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}
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/* SPI clock output divider is: divider = CKOUTDIV + 1 */
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priv->spi_clk_out_div = divider - 1;
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priv->dfsdm.spi_master_freq = clk_freq / (priv->spi_clk_out_div + 1);
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if (rem) {
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dev_warn(&pdev->dev, "SPI clock not accurate\n");
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dev_warn(&pdev->dev, "%ld = %d * %d + %d\n",
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clk_freq, spi_freq, priv->spi_clk_out_div + 1, rem);
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}
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return 0;
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};
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static const struct of_device_id stm32_dfsdm_of_match[] = {
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{
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.compatible = "st,stm32h7-dfsdm",
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.data = &stm32h7_dfsdm_data,
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},
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{
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.compatible = "st,stm32mp1-dfsdm",
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.data = &stm32mp1_dfsdm_data,
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, stm32_dfsdm_of_match);
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static int stm32_dfsdm_probe(struct platform_device *pdev)
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{
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struct dfsdm_priv *priv;
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const struct stm32_dfsdm_dev_data *dev_data;
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struct stm32_dfsdm *dfsdm;
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int ret;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->pdev = pdev;
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dev_data = of_device_get_match_data(&pdev->dev);
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dfsdm = &priv->dfsdm;
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dfsdm->fl_list = devm_kcalloc(&pdev->dev, dev_data->num_filters,
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sizeof(*dfsdm->fl_list), GFP_KERNEL);
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if (!dfsdm->fl_list)
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return -ENOMEM;
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dfsdm->num_fls = dev_data->num_filters;
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dfsdm->ch_list = devm_kcalloc(&pdev->dev, dev_data->num_channels,
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sizeof(*dfsdm->ch_list),
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GFP_KERNEL);
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if (!dfsdm->ch_list)
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return -ENOMEM;
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dfsdm->num_chs = dev_data->num_channels;
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ret = stm32_dfsdm_parse_of(pdev, priv);
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if (ret < 0)
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return ret;
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dfsdm->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dfsdm",
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dfsdm->base,
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dev_data->regmap_cfg);
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if (IS_ERR(dfsdm->regmap)) {
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ret = PTR_ERR(dfsdm->regmap);
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dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
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__func__, ret);
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return ret;
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}
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platform_set_drvdata(pdev, dfsdm);
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ret = stm32_dfsdm_clk_prepare_enable(dfsdm);
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if (ret) {
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dev_err(&pdev->dev, "Failed to start clock\n");
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return ret;
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}
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pm_runtime_get_noresume(&pdev->dev);
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
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if (ret)
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goto pm_put;
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pm_runtime_put(&pdev->dev);
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return 0;
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pm_put:
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pm_runtime_disable(&pdev->dev);
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pm_runtime_set_suspended(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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stm32_dfsdm_clk_disable_unprepare(dfsdm);
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return ret;
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}
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static int stm32_dfsdm_core_remove(struct platform_device *pdev)
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{
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struct stm32_dfsdm *dfsdm = platform_get_drvdata(pdev);
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pm_runtime_get_sync(&pdev->dev);
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of_platform_depopulate(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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pm_runtime_set_suspended(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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stm32_dfsdm_clk_disable_unprepare(dfsdm);
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return 0;
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}
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static int __maybe_unused stm32_dfsdm_core_suspend(struct device *dev)
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{
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struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
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struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
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int ret;
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ret = pm_runtime_force_suspend(dev);
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if (ret)
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return ret;
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/* Balance devm_regmap_init_mmio_clk() clk_prepare() */
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clk_unprepare(priv->clk);
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return pinctrl_pm_select_sleep_state(dev);
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}
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static int __maybe_unused stm32_dfsdm_core_resume(struct device *dev)
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{
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struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
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struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
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int ret;
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ret = pinctrl_pm_select_default_state(dev);
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if (ret)
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return ret;
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ret = clk_prepare(priv->clk);
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if (ret)
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return ret;
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return pm_runtime_force_resume(dev);
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}
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static int __maybe_unused stm32_dfsdm_core_runtime_suspend(struct device *dev)
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{
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struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
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stm32_dfsdm_clk_disable_unprepare(dfsdm);
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return 0;
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}
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static int __maybe_unused stm32_dfsdm_core_runtime_resume(struct device *dev)
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{
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struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
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return stm32_dfsdm_clk_prepare_enable(dfsdm);
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}
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static const struct dev_pm_ops stm32_dfsdm_core_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(stm32_dfsdm_core_suspend,
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stm32_dfsdm_core_resume)
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SET_RUNTIME_PM_OPS(stm32_dfsdm_core_runtime_suspend,
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stm32_dfsdm_core_runtime_resume,
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NULL)
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};
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static struct platform_driver stm32_dfsdm_driver = {
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.probe = stm32_dfsdm_probe,
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.remove = stm32_dfsdm_core_remove,
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.driver = {
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.name = "stm32-dfsdm",
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.of_match_table = stm32_dfsdm_of_match,
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.pm = &stm32_dfsdm_core_pm_ops,
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},
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};
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module_platform_driver(stm32_dfsdm_driver);
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MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
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MODULE_DESCRIPTION("STMicroelectronics STM32 dfsdm driver");
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MODULE_LICENSE("GPL v2");
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