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![Alexandru Ardelean](/assets/img/avatar_default.png)
All drivers that already call devm_iio_kfifo_allocate() & iio_device_attach_buffer() are simple to convert to iio_device_attach_kfifo_buffer() in a single go. This change does that; the unwind order is preserved. What is important, is that the devm_iio_kfifo_buffer_setup() be called after the indio_dev->modes is assigned, to make sure that INDIO_BUFFER_SOFTWARE flag is set and not overridden by the assignment to indio_dev->modes. Also, the INDIO_BUFFER_SOFTWARE has been removed from the assignments of 'indio_dev->modes' because it is set by devm_iio_kfifo_buffer_setup(). Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Matt Ranostay <matt.ranostay@konsulko.com>x Link: https://lore.kernel.org/r/20210215104043.91251-4-alexandru.ardelean@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
719 lines
18 KiB
C
719 lines
18 KiB
C
/*
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* TI ADC MFD driver
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/iio/iio.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/iio/machine.h>
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#include <linux/iio/driver.h>
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#include <linux/mfd/ti_am335x_tscadc.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/kfifo_buf.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#define DMA_BUFFER_SIZE SZ_2K
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struct tiadc_dma {
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struct dma_slave_config conf;
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struct dma_chan *chan;
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dma_addr_t addr;
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dma_cookie_t cookie;
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u8 *buf;
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int current_period;
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int period_size;
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u8 fifo_thresh;
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};
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struct tiadc_device {
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struct ti_tscadc_dev *mfd_tscadc;
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struct tiadc_dma dma;
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struct mutex fifo1_lock; /* to protect fifo access */
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int channels;
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int total_ch_enabled;
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u8 channel_line[8];
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u8 channel_step[8];
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int buffer_en_ch_steps;
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u16 data[8];
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u32 open_delay[8], sample_delay[8], step_avg[8];
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};
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static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg)
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{
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return readl(adc->mfd_tscadc->tscadc_base + reg);
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}
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static void tiadc_writel(struct tiadc_device *adc, unsigned int reg,
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unsigned int val)
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{
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writel(val, adc->mfd_tscadc->tscadc_base + reg);
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}
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static u32 get_adc_step_mask(struct tiadc_device *adc_dev)
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{
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u32 step_en;
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step_en = ((1 << adc_dev->channels) - 1);
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step_en <<= TOTAL_STEPS - adc_dev->channels + 1;
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return step_en;
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}
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static u32 get_adc_chan_step_mask(struct tiadc_device *adc_dev,
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struct iio_chan_spec const *chan)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) {
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if (chan->channel == adc_dev->channel_line[i]) {
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u32 step;
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step = adc_dev->channel_step[i];
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/* +1 for the charger */
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return 1 << (step + 1);
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}
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}
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WARN_ON(1);
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return 0;
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}
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static u32 get_adc_step_bit(struct tiadc_device *adc_dev, int chan)
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{
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return 1 << adc_dev->channel_step[chan];
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}
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static void tiadc_step_config(struct iio_dev *indio_dev)
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{
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struct tiadc_device *adc_dev = iio_priv(indio_dev);
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struct device *dev = adc_dev->mfd_tscadc->dev;
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unsigned int stepconfig;
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int i, steps = 0;
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/*
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* There are 16 configurable steps and 8 analog input
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* lines available which are shared between Touchscreen and ADC.
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*
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* Steps forwards i.e. from 0 towards 16 are used by ADC
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* depending on number of input lines needed.
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* Channel would represent which analog input
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* needs to be given to ADC to digitalize data.
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*/
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for (i = 0; i < adc_dev->channels; i++) {
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int chan;
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chan = adc_dev->channel_line[i];
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if (adc_dev->step_avg[i] > STEPCONFIG_AVG_16) {
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dev_warn(dev, "chan %d step_avg truncating to %d\n",
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chan, STEPCONFIG_AVG_16);
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adc_dev->step_avg[i] = STEPCONFIG_AVG_16;
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}
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if (adc_dev->step_avg[i])
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stepconfig =
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STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) |
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STEPCONFIG_FIFO1;
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else
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stepconfig = STEPCONFIG_FIFO1;
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if (iio_buffer_enabled(indio_dev))
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stepconfig |= STEPCONFIG_MODE_SWCNT;
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tiadc_writel(adc_dev, REG_STEPCONFIG(steps),
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stepconfig | STEPCONFIG_INP(chan) |
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STEPCONFIG_INM_ADCREFM |
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STEPCONFIG_RFP_VREFP |
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STEPCONFIG_RFM_VREFN);
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if (adc_dev->open_delay[i] > STEPDELAY_OPEN_MASK) {
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dev_warn(dev, "chan %d open delay truncating to 0x3FFFF\n",
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chan);
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adc_dev->open_delay[i] = STEPDELAY_OPEN_MASK;
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}
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if (adc_dev->sample_delay[i] > 0xFF) {
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dev_warn(dev, "chan %d sample delay truncating to 0xFF\n",
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chan);
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adc_dev->sample_delay[i] = 0xFF;
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}
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tiadc_writel(adc_dev, REG_STEPDELAY(steps),
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STEPDELAY_OPEN(adc_dev->open_delay[i]) |
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STEPDELAY_SAMPLE(adc_dev->sample_delay[i]));
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adc_dev->channel_step[i] = steps;
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steps++;
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}
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}
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static irqreturn_t tiadc_irq_h(int irq, void *private)
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{
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struct iio_dev *indio_dev = private;
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struct tiadc_device *adc_dev = iio_priv(indio_dev);
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unsigned int status, config, adc_fsm;
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unsigned short count = 0;
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status = tiadc_readl(adc_dev, REG_IRQSTATUS);
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/*
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* ADC and touchscreen share the IRQ line.
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* FIFO0 interrupts are used by TSC. Handle FIFO1 IRQs here only
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*/
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if (status & IRQENB_FIFO1OVRRUN) {
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/* FIFO Overrun. Clear flag. Disable/Enable ADC to recover */
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config = tiadc_readl(adc_dev, REG_CTRL);
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config &= ~(CNTRLREG_TSCSSENB);
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tiadc_writel(adc_dev, REG_CTRL, config);
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tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1OVRRUN
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| IRQENB_FIFO1UNDRFLW | IRQENB_FIFO1THRES);
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/* wait for idle state.
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* ADC needs to finish the current conversion
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* before disabling the module
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*/
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do {
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adc_fsm = tiadc_readl(adc_dev, REG_ADCFSM);
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} while (adc_fsm != 0x10 && count++ < 100);
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tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_TSCSSENB));
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return IRQ_HANDLED;
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} else if (status & IRQENB_FIFO1THRES) {
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/* Disable irq and wake worker thread */
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tiadc_writel(adc_dev, REG_IRQCLR, IRQENB_FIFO1THRES);
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return IRQ_WAKE_THREAD;
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}
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return IRQ_NONE;
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}
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static irqreturn_t tiadc_worker_h(int irq, void *private)
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{
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struct iio_dev *indio_dev = private;
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struct tiadc_device *adc_dev = iio_priv(indio_dev);
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int i, k, fifo1count, read;
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u16 *data = adc_dev->data;
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fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
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for (k = 0; k < fifo1count; k = k + i) {
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for (i = 0; i < (indio_dev->scan_bytes)/2; i++) {
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read = tiadc_readl(adc_dev, REG_FIFO1);
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data[i] = read & FIFOREAD_DATA_MASK;
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}
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iio_push_to_buffers(indio_dev, (u8 *) data);
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}
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tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES);
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tiadc_writel(adc_dev, REG_IRQENABLE, IRQENB_FIFO1THRES);
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return IRQ_HANDLED;
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}
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static void tiadc_dma_rx_complete(void *param)
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{
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struct iio_dev *indio_dev = param;
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struct tiadc_device *adc_dev = iio_priv(indio_dev);
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struct tiadc_dma *dma = &adc_dev->dma;
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u8 *data;
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int i;
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data = dma->buf + dma->current_period * dma->period_size;
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dma->current_period = 1 - dma->current_period; /* swap the buffer ID */
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for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) {
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iio_push_to_buffers(indio_dev, data);
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data += indio_dev->scan_bytes;
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}
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}
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static int tiadc_start_dma(struct iio_dev *indio_dev)
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{
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struct tiadc_device *adc_dev = iio_priv(indio_dev);
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struct tiadc_dma *dma = &adc_dev->dma;
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struct dma_async_tx_descriptor *desc;
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dma->current_period = 0; /* We start to fill period 0 */
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/*
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* Make the fifo thresh as the multiple of total number of
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* channels enabled, so make sure that cyclic DMA period
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* length is also a multiple of total number of channels
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* enabled. This ensures that no invalid data is reported
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* to the stack via iio_push_to_buffers().
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*/
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dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1,
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adc_dev->total_ch_enabled) - 1;
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/* Make sure that period length is multiple of fifo thresh level */
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dma->period_size = rounddown(DMA_BUFFER_SIZE / 2,
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(dma->fifo_thresh + 1) * sizeof(u16));
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dma->conf.src_maxburst = dma->fifo_thresh + 1;
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dmaengine_slave_config(dma->chan, &dma->conf);
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desc = dmaengine_prep_dma_cyclic(dma->chan, dma->addr,
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dma->period_size * 2,
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dma->period_size, DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT);
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if (!desc)
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return -EBUSY;
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desc->callback = tiadc_dma_rx_complete;
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desc->callback_param = indio_dev;
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dma->cookie = dmaengine_submit(desc);
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dma_async_issue_pending(dma->chan);
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tiadc_writel(adc_dev, REG_FIFO1THR, dma->fifo_thresh);
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tiadc_writel(adc_dev, REG_DMA1REQ, dma->fifo_thresh);
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tiadc_writel(adc_dev, REG_DMAENABLE_SET, DMA_FIFO1);
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return 0;
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}
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static int tiadc_buffer_preenable(struct iio_dev *indio_dev)
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{
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struct tiadc_device *adc_dev = iio_priv(indio_dev);
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int i, fifo1count;
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tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES |
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IRQENB_FIFO1OVRRUN |
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IRQENB_FIFO1UNDRFLW));
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/* Flush FIFO. Needed in corner cases in simultaneous tsc/adc use */
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fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
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for (i = 0; i < fifo1count; i++)
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tiadc_readl(adc_dev, REG_FIFO1);
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return 0;
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}
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static int tiadc_buffer_postenable(struct iio_dev *indio_dev)
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{
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struct tiadc_device *adc_dev = iio_priv(indio_dev);
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struct tiadc_dma *dma = &adc_dev->dma;
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unsigned int irq_enable;
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unsigned int enb = 0;
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u8 bit;
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tiadc_step_config(indio_dev);
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for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels) {
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enb |= (get_adc_step_bit(adc_dev, bit) << 1);
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adc_dev->total_ch_enabled++;
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}
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adc_dev->buffer_en_ch_steps = enb;
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if (dma->chan)
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tiadc_start_dma(indio_dev);
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am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, enb);
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tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES
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| IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW);
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irq_enable = IRQENB_FIFO1OVRRUN;
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if (!dma->chan)
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irq_enable |= IRQENB_FIFO1THRES;
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tiadc_writel(adc_dev, REG_IRQENABLE, irq_enable);
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return 0;
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}
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static int tiadc_buffer_predisable(struct iio_dev *indio_dev)
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{
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struct tiadc_device *adc_dev = iio_priv(indio_dev);
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struct tiadc_dma *dma = &adc_dev->dma;
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int fifo1count, i;
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tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES |
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IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW));
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am335x_tsc_se_clr(adc_dev->mfd_tscadc, adc_dev->buffer_en_ch_steps);
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adc_dev->buffer_en_ch_steps = 0;
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adc_dev->total_ch_enabled = 0;
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if (dma->chan) {
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tiadc_writel(adc_dev, REG_DMAENABLE_CLEAR, 0x2);
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dmaengine_terminate_async(dma->chan);
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}
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/* Flush FIFO of leftover data in the time it takes to disable adc */
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fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
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for (i = 0; i < fifo1count; i++)
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tiadc_readl(adc_dev, REG_FIFO1);
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return 0;
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}
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static int tiadc_buffer_postdisable(struct iio_dev *indio_dev)
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{
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tiadc_step_config(indio_dev);
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return 0;
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}
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static const struct iio_buffer_setup_ops tiadc_buffer_setup_ops = {
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.preenable = &tiadc_buffer_preenable,
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.postenable = &tiadc_buffer_postenable,
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.predisable = &tiadc_buffer_predisable,
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.postdisable = &tiadc_buffer_postdisable,
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};
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static int tiadc_iio_buffered_hardware_setup(struct device *dev,
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struct iio_dev *indio_dev,
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irqreturn_t (*pollfunc_bh)(int irq, void *p),
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irqreturn_t (*pollfunc_th)(int irq, void *p),
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int irq,
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unsigned long flags,
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const struct iio_buffer_setup_ops *setup_ops)
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{
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int ret;
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ret = devm_iio_kfifo_buffer_setup(dev, indio_dev,
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INDIO_BUFFER_SOFTWARE,
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setup_ops);
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if (ret)
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return ret;
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return devm_request_threaded_irq(dev, irq, pollfunc_th, pollfunc_bh,
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flags, indio_dev->name, indio_dev);
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}
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static const char * const chan_name_ain[] = {
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"AIN0",
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"AIN1",
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"AIN2",
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"AIN3",
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"AIN4",
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"AIN5",
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"AIN6",
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"AIN7",
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};
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static int tiadc_channel_init(struct device *dev, struct iio_dev *indio_dev,
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int channels)
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{
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struct tiadc_device *adc_dev = iio_priv(indio_dev);
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struct iio_chan_spec *chan_array;
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struct iio_chan_spec *chan;
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int i;
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indio_dev->num_channels = channels;
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chan_array = devm_kcalloc(dev, channels, sizeof(*chan_array),
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GFP_KERNEL);
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if (chan_array == NULL)
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return -ENOMEM;
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chan = chan_array;
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for (i = 0; i < channels; i++, chan++) {
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chan->type = IIO_VOLTAGE;
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chan->indexed = 1;
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chan->channel = adc_dev->channel_line[i];
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chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
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chan->datasheet_name = chan_name_ain[chan->channel];
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chan->scan_index = i;
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chan->scan_type.sign = 'u';
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chan->scan_type.realbits = 12;
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chan->scan_type.storagebits = 16;
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}
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indio_dev->channels = chan_array;
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return 0;
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}
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static int tiadc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct tiadc_device *adc_dev = iio_priv(indio_dev);
|
|
int ret = IIO_VAL_INT;
|
|
int i, map_val;
|
|
unsigned int fifo1count, read, stepid;
|
|
bool found = false;
|
|
u32 step_en;
|
|
unsigned long timeout;
|
|
|
|
if (iio_buffer_enabled(indio_dev))
|
|
return -EBUSY;
|
|
|
|
step_en = get_adc_chan_step_mask(adc_dev, chan);
|
|
if (!step_en)
|
|
return -EINVAL;
|
|
|
|
mutex_lock(&adc_dev->fifo1_lock);
|
|
fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
|
|
while (fifo1count--)
|
|
tiadc_readl(adc_dev, REG_FIFO1);
|
|
|
|
am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en);
|
|
|
|
timeout = jiffies + msecs_to_jiffies
|
|
(IDLE_TIMEOUT * adc_dev->channels);
|
|
/* Wait for Fifo threshold interrupt */
|
|
while (1) {
|
|
fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
|
|
if (fifo1count)
|
|
break;
|
|
|
|
if (time_after(jiffies, timeout)) {
|
|
am335x_tsc_se_adc_done(adc_dev->mfd_tscadc);
|
|
ret = -EAGAIN;
|
|
goto err_unlock;
|
|
}
|
|
}
|
|
map_val = adc_dev->channel_step[chan->scan_index];
|
|
|
|
/*
|
|
* We check the complete FIFO. We programmed just one entry but in case
|
|
* something went wrong we left empty handed (-EAGAIN previously) and
|
|
* then the value apeared somehow in the FIFO we would have two entries.
|
|
* Therefore we read every item and keep only the latest version of the
|
|
* requested channel.
|
|
*/
|
|
for (i = 0; i < fifo1count; i++) {
|
|
read = tiadc_readl(adc_dev, REG_FIFO1);
|
|
stepid = read & FIFOREAD_CHNLID_MASK;
|
|
stepid = stepid >> 0x10;
|
|
|
|
if (stepid == map_val) {
|
|
read = read & FIFOREAD_DATA_MASK;
|
|
found = true;
|
|
*val = (u16) read;
|
|
}
|
|
}
|
|
am335x_tsc_se_adc_done(adc_dev->mfd_tscadc);
|
|
|
|
if (!found)
|
|
ret = -EBUSY;
|
|
|
|
err_unlock:
|
|
mutex_unlock(&adc_dev->fifo1_lock);
|
|
return ret;
|
|
}
|
|
|
|
static const struct iio_info tiadc_info = {
|
|
.read_raw = &tiadc_read_raw,
|
|
};
|
|
|
|
static int tiadc_request_dma(struct platform_device *pdev,
|
|
struct tiadc_device *adc_dev)
|
|
{
|
|
struct tiadc_dma *dma = &adc_dev->dma;
|
|
dma_cap_mask_t mask;
|
|
|
|
/* Default slave configuration parameters */
|
|
dma->conf.direction = DMA_DEV_TO_MEM;
|
|
dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
|
|
dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1;
|
|
|
|
dma_cap_zero(mask);
|
|
dma_cap_set(DMA_CYCLIC, mask);
|
|
|
|
/* Get a channel for RX */
|
|
dma->chan = dma_request_chan(adc_dev->mfd_tscadc->dev, "fifo1");
|
|
if (IS_ERR(dma->chan)) {
|
|
int ret = PTR_ERR(dma->chan);
|
|
|
|
dma->chan = NULL;
|
|
return ret;
|
|
}
|
|
|
|
/* RX buffer */
|
|
dma->buf = dma_alloc_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
|
|
&dma->addr, GFP_KERNEL);
|
|
if (!dma->buf)
|
|
goto err;
|
|
|
|
return 0;
|
|
err:
|
|
dma_release_channel(dma->chan);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static int tiadc_parse_dt(struct platform_device *pdev,
|
|
struct tiadc_device *adc_dev)
|
|
{
|
|
struct device_node *node = pdev->dev.of_node;
|
|
struct property *prop;
|
|
const __be32 *cur;
|
|
int channels = 0;
|
|
u32 val;
|
|
|
|
of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
|
|
adc_dev->channel_line[channels] = val;
|
|
|
|
/* Set Default values for optional DT parameters */
|
|
adc_dev->open_delay[channels] = STEPCONFIG_OPENDLY;
|
|
adc_dev->sample_delay[channels] = STEPCONFIG_SAMPLEDLY;
|
|
adc_dev->step_avg[channels] = 16;
|
|
|
|
channels++;
|
|
}
|
|
|
|
of_property_read_u32_array(node, "ti,chan-step-avg",
|
|
adc_dev->step_avg, channels);
|
|
of_property_read_u32_array(node, "ti,chan-step-opendelay",
|
|
adc_dev->open_delay, channels);
|
|
of_property_read_u32_array(node, "ti,chan-step-sampledelay",
|
|
adc_dev->sample_delay, channels);
|
|
|
|
adc_dev->channels = channels;
|
|
return 0;
|
|
}
|
|
|
|
static int tiadc_probe(struct platform_device *pdev)
|
|
{
|
|
struct iio_dev *indio_dev;
|
|
struct tiadc_device *adc_dev;
|
|
struct device_node *node = pdev->dev.of_node;
|
|
int err;
|
|
|
|
if (!node) {
|
|
dev_err(&pdev->dev, "Could not find valid DT data.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
|
|
if (indio_dev == NULL) {
|
|
dev_err(&pdev->dev, "failed to allocate iio device\n");
|
|
return -ENOMEM;
|
|
}
|
|
adc_dev = iio_priv(indio_dev);
|
|
|
|
adc_dev->mfd_tscadc = ti_tscadc_dev_get(pdev);
|
|
tiadc_parse_dt(pdev, adc_dev);
|
|
|
|
indio_dev->name = dev_name(&pdev->dev);
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
indio_dev->info = &tiadc_info;
|
|
|
|
tiadc_step_config(indio_dev);
|
|
tiadc_writel(adc_dev, REG_FIFO1THR, FIFO1_THRESHOLD);
|
|
mutex_init(&adc_dev->fifo1_lock);
|
|
|
|
err = tiadc_channel_init(&pdev->dev, indio_dev, adc_dev->channels);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = tiadc_iio_buffered_hardware_setup(&pdev->dev, indio_dev,
|
|
&tiadc_worker_h,
|
|
&tiadc_irq_h,
|
|
adc_dev->mfd_tscadc->irq,
|
|
IRQF_SHARED,
|
|
&tiadc_buffer_setup_ops);
|
|
|
|
if (err)
|
|
goto err_free_channels;
|
|
|
|
err = iio_device_register(indio_dev);
|
|
if (err)
|
|
goto err_buffer_unregister;
|
|
|
|
platform_set_drvdata(pdev, indio_dev);
|
|
|
|
err = tiadc_request_dma(pdev, adc_dev);
|
|
if (err && err == -EPROBE_DEFER)
|
|
goto err_dma;
|
|
|
|
return 0;
|
|
|
|
err_dma:
|
|
iio_device_unregister(indio_dev);
|
|
err_buffer_unregister:
|
|
err_free_channels:
|
|
return err;
|
|
}
|
|
|
|
static int tiadc_remove(struct platform_device *pdev)
|
|
{
|
|
struct iio_dev *indio_dev = platform_get_drvdata(pdev);
|
|
struct tiadc_device *adc_dev = iio_priv(indio_dev);
|
|
struct tiadc_dma *dma = &adc_dev->dma;
|
|
u32 step_en;
|
|
|
|
if (dma->chan) {
|
|
dma_free_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
|
|
dma->buf, dma->addr);
|
|
dma_release_channel(dma->chan);
|
|
}
|
|
iio_device_unregister(indio_dev);
|
|
|
|
step_en = get_adc_step_mask(adc_dev);
|
|
am335x_tsc_se_clr(adc_dev->mfd_tscadc, step_en);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused tiadc_suspend(struct device *dev)
|
|
{
|
|
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
|
struct tiadc_device *adc_dev = iio_priv(indio_dev);
|
|
unsigned int idle;
|
|
|
|
idle = tiadc_readl(adc_dev, REG_CTRL);
|
|
idle &= ~(CNTRLREG_TSCSSENB);
|
|
tiadc_writel(adc_dev, REG_CTRL, (idle |
|
|
CNTRLREG_POWERDOWN));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused tiadc_resume(struct device *dev)
|
|
{
|
|
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
|
struct tiadc_device *adc_dev = iio_priv(indio_dev);
|
|
unsigned int restore;
|
|
|
|
/* Make sure ADC is powered up */
|
|
restore = tiadc_readl(adc_dev, REG_CTRL);
|
|
restore &= ~(CNTRLREG_POWERDOWN);
|
|
tiadc_writel(adc_dev, REG_CTRL, restore);
|
|
|
|
tiadc_step_config(indio_dev);
|
|
am335x_tsc_se_set_cache(adc_dev->mfd_tscadc,
|
|
adc_dev->buffer_en_ch_steps);
|
|
return 0;
|
|
}
|
|
|
|
static SIMPLE_DEV_PM_OPS(tiadc_pm_ops, tiadc_suspend, tiadc_resume);
|
|
|
|
static const struct of_device_id ti_adc_dt_ids[] = {
|
|
{ .compatible = "ti,am3359-adc", },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ti_adc_dt_ids);
|
|
|
|
static struct platform_driver tiadc_driver = {
|
|
.driver = {
|
|
.name = "TI-am335x-adc",
|
|
.pm = &tiadc_pm_ops,
|
|
.of_match_table = ti_adc_dt_ids,
|
|
},
|
|
.probe = tiadc_probe,
|
|
.remove = tiadc_remove,
|
|
};
|
|
module_platform_driver(tiadc_driver);
|
|
|
|
MODULE_DESCRIPTION("TI ADC controller driver");
|
|
MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
|
|
MODULE_LICENSE("GPL");
|