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b766e3b0d5
The system controller node manages the CTRL_MMR0 region. Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Tero Kristo <t-kristo@ti.com>
53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This header provides constants for J721E WIZ.
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*/
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#ifndef _DT_BINDINGS_J721E_WIZ
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#define _DT_BINDINGS_J721E_WIZ
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#define SERDES0_LANE0_QSGMII_LANE1 0x0
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#define SERDES0_LANE0_PCIE0_LANE0 0x1
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#define SERDES0_LANE0_USB3_0_SWAP 0x2
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#define SERDES0_LANE1_QSGMII_LANE2 0x0
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#define SERDES0_LANE1_PCIE0_LANE1 0x1
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#define SERDES0_LANE1_USB3_0 0x2
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#define SERDES1_LANE0_QSGMII_LANE3 0x0
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#define SERDES1_LANE0_PCIE1_LANE0 0x1
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#define SERDES1_LANE0_USB3_1_SWAP 0x2
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#define SERDES1_LANE0_SGMII_LANE0 0x3
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#define SERDES1_LANE1_QSGMII_LANE4 0x0
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#define SERDES1_LANE1_PCIE1_LANE1 0x1
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#define SERDES1_LANE1_USB3_1 0x2
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#define SERDES1_LANE1_SGMII_LANE1 0x3
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#define SERDES2_LANE0_PCIE2_LANE0 0x1
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#define SERDES2_LANE0_SGMII_LANE0 0x3
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#define SERDES2_LANE0_USB3_1_SWAP 0x2
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#define SERDES2_LANE1_PCIE2_LANE1 0x1
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#define SERDES2_LANE1_USB3_1 0x2
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#define SERDES2_LANE1_SGMII_LANE1 0x3
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#define SERDES3_LANE0_PCIE3_LANE0 0x1
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#define SERDES3_LANE0_USB3_0_SWAP 0x2
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#define SERDES3_LANE1_PCIE3_LANE1 0x1
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#define SERDES3_LANE1_USB3_0 0x2
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#define SERDES4_LANE0_EDP_LANE0 0x0
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#define SERDES4_LANE0_QSGMII_LANE5 0x2
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#define SERDES4_LANE1_EDP_LANE1 0x0
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#define SERDES4_LANE1_QSGMII_LANE6 0x2
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#define SERDES4_LANE2_EDP_LANE2 0x0
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#define SERDES4_LANE2_QSGMII_LANE7 0x2
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#define SERDES4_LANE3_EDP_LANE3 0x0
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#define SERDES4_LANE3_QSGMII_LANE8 0x2
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#endif /* _DT_BINDINGS_J721E_WIZ */
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