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5a8781607e
Currently, host_rsp is cached on a per-vCPU basis, i.e. it's stored in struct vcpu_vmx. In non-nested usage the caching is for all intents and purposes 100% effective, e.g. only the first VMLAUNCH needs to synchronize VMCS.HOST_RSP since the call stack to vmx_vcpu_run() is identical each and every time. But when running a nested guest, KVM must invalidate the cache when switching the current VMCS as it can't guarantee the new VMCS has the same HOST_RSP as the previous VMCS. In other words, the cache loses almost all of its efficacy when running a nested VM. Move host_rsp to struct vmcs_host_state, which is per-VMCS, so that it is cached on a per-VMCS basis and restores its 100% hit rate when nested VMs are in play. Note that the host_rsp cache for vmcs02 essentially "breaks" when nested early checks are enabled as nested_vmx_check_vmentry_hw() will see a different RSP at the time of its VM-Enter. While it's possible to avoid even that VMCS.HOST_RSP synchronization, e.g. by employing a dedicated VM-Exit stack, there is little motivation for doing so as the overhead of two VMWRITEs (~55 cycles) is dwarfed by the overhead of the extra VMX transition (600+ cycles) and is a proverbial drop in the ocean relative to the total cost of a nested transtion (10s of thousands of cycles). Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Reviewed-by: Jim Mattson <jmattson@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
137 lines
3.2 KiB
C
137 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_VMX_VMCS_H
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#define __KVM_X86_VMX_VMCS_H
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#include <linux/ktime.h>
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#include <linux/list.h>
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#include <linux/nospec.h>
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#include <asm/kvm.h>
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#include <asm/vmx.h>
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#include "capabilities.h"
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struct vmcs_hdr {
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u32 revision_id:31;
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u32 shadow_vmcs:1;
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};
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struct vmcs {
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struct vmcs_hdr hdr;
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u32 abort;
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char data[0];
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};
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DECLARE_PER_CPU(struct vmcs *, current_vmcs);
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/*
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* vmcs_host_state tracks registers that are loaded from the VMCS on VMEXIT
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* and whose values change infrequently, but are not constant. I.e. this is
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* used as a write-through cache of the corresponding VMCS fields.
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*/
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struct vmcs_host_state {
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unsigned long cr3; /* May not match real cr3 */
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unsigned long cr4; /* May not match real cr4 */
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unsigned long gs_base;
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unsigned long fs_base;
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unsigned long rsp;
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u16 fs_sel, gs_sel, ldt_sel;
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#ifdef CONFIG_X86_64
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u16 ds_sel, es_sel;
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#endif
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};
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/*
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* Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
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* remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
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* loaded on this CPU (so we can clear them if the CPU goes down).
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*/
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struct loaded_vmcs {
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struct vmcs *vmcs;
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struct vmcs *shadow_vmcs;
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int cpu;
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bool launched;
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bool nmi_known_unmasked;
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bool hv_timer_armed;
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/* Support for vnmi-less CPUs */
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int soft_vnmi_blocked;
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ktime_t entry_time;
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s64 vnmi_blocked_time;
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unsigned long *msr_bitmap;
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struct list_head loaded_vmcss_on_cpu_link;
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struct vmcs_host_state host_state;
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};
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static inline bool is_exception_n(u32 intr_info, u8 vector)
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{
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return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
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INTR_INFO_VALID_MASK)) ==
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(INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
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}
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static inline bool is_debug(u32 intr_info)
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{
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return is_exception_n(intr_info, DB_VECTOR);
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}
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static inline bool is_breakpoint(u32 intr_info)
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{
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return is_exception_n(intr_info, BP_VECTOR);
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}
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static inline bool is_page_fault(u32 intr_info)
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{
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return is_exception_n(intr_info, PF_VECTOR);
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}
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static inline bool is_invalid_opcode(u32 intr_info)
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{
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return is_exception_n(intr_info, UD_VECTOR);
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}
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static inline bool is_gp_fault(u32 intr_info)
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{
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return is_exception_n(intr_info, GP_VECTOR);
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}
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static inline bool is_machine_check(u32 intr_info)
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{
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return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
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INTR_INFO_VALID_MASK)) ==
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(INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
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}
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/* Undocumented: icebp/int1 */
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static inline bool is_icebp(u32 intr_info)
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{
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return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
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== (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
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}
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static inline bool is_nmi(u32 intr_info)
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{
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return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
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== (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
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}
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enum vmcs_field_width {
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VMCS_FIELD_WIDTH_U16 = 0,
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VMCS_FIELD_WIDTH_U64 = 1,
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VMCS_FIELD_WIDTH_U32 = 2,
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VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
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};
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static inline int vmcs_field_width(unsigned long field)
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{
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if (0x1 & field) /* the *_HIGH fields are all 32 bit */
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return VMCS_FIELD_WIDTH_U32;
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return (field >> 13) & 0x3;
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}
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static inline int vmcs_field_readonly(unsigned long field)
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{
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return (((field >> 10) & 0x3) == 1);
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}
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#endif /* __KVM_X86_VMX_VMCS_H */
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