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0b56e9a7e8
Adding vendor specific directories in phy to group phy drivers under their respective vendor umbrella. Also updated the MAINTAINERS file to reflect the correct directory structure for phy drivers. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: David S. Miller <davem@davemloft.net> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Stephen Boyd <stephen.boyd@linaro.org> Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-omap@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-usb@vger.kernel.org Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
378 lines
10 KiB
C
378 lines
10 KiB
C
/*
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* Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4x12 support
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* Author: Kamil Debski <k.debski@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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#include "phy-samsung-usb2.h"
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/* Exynos USB PHY registers */
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/* PHY power control */
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#define EXYNOS_4x12_UPHYPWR 0x0
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#define EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND BIT(0)
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#define EXYNOS_4x12_UPHYPWR_PHY0_PWR BIT(3)
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#define EXYNOS_4x12_UPHYPWR_PHY0_OTG_PWR BIT(4)
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#define EXYNOS_4x12_UPHYPWR_PHY0_SLEEP BIT(5)
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#define EXYNOS_4x12_UPHYPWR_PHY0 ( \
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EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND | \
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EXYNOS_4x12_UPHYPWR_PHY0_PWR | \
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EXYNOS_4x12_UPHYPWR_PHY0_OTG_PWR | \
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EXYNOS_4x12_UPHYPWR_PHY0_SLEEP)
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#define EXYNOS_4x12_UPHYPWR_PHY1_SUSPEND BIT(6)
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#define EXYNOS_4x12_UPHYPWR_PHY1_PWR BIT(7)
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#define EXYNOS_4x12_UPHYPWR_PHY1_SLEEP BIT(8)
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#define EXYNOS_4x12_UPHYPWR_PHY1 ( \
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EXYNOS_4x12_UPHYPWR_PHY1_SUSPEND | \
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EXYNOS_4x12_UPHYPWR_PHY1_PWR | \
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EXYNOS_4x12_UPHYPWR_PHY1_SLEEP)
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#define EXYNOS_4x12_UPHYPWR_HSIC0_SUSPEND BIT(9)
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#define EXYNOS_4x12_UPHYPWR_HSIC0_PWR BIT(10)
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#define EXYNOS_4x12_UPHYPWR_HSIC0_SLEEP BIT(11)
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#define EXYNOS_4x12_UPHYPWR_HSIC0 ( \
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EXYNOS_4x12_UPHYPWR_HSIC0_SUSPEND | \
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EXYNOS_4x12_UPHYPWR_HSIC0_PWR | \
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EXYNOS_4x12_UPHYPWR_HSIC0_SLEEP)
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#define EXYNOS_4x12_UPHYPWR_HSIC1_SUSPEND BIT(12)
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#define EXYNOS_4x12_UPHYPWR_HSIC1_PWR BIT(13)
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#define EXYNOS_4x12_UPHYPWR_HSIC1_SLEEP BIT(14)
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#define EXYNOS_4x12_UPHYPWR_HSIC1 ( \
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EXYNOS_4x12_UPHYPWR_HSIC1_SUSPEND | \
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EXYNOS_4x12_UPHYPWR_HSIC1_PWR | \
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EXYNOS_4x12_UPHYPWR_HSIC1_SLEEP)
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/* PHY clock control */
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#define EXYNOS_4x12_UPHYCLK 0x4
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#define EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK (0x7 << 0)
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#define EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET 0
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#define EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6 (0x0 << 0)
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#define EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ (0x1 << 0)
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#define EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
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#define EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2 (0x3 << 0)
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#define EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ (0x4 << 0)
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#define EXYNOS_4x12_UPHYCLK_PHYFSEL_24MHZ (0x5 << 0)
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#define EXYNOS_4x12_UPHYCLK_PHYFSEL_50MHZ (0x7 << 0)
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#define EXYNOS_3250_UPHYCLK_REFCLKSEL (0x2 << 8)
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#define EXYNOS_4x12_UPHYCLK_PHY0_ID_PULLUP BIT(3)
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#define EXYNOS_4x12_UPHYCLK_PHY0_COMMON_ON BIT(4)
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#define EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON BIT(7)
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#define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_MASK (0x7f << 10)
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#define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_OFFSET 10
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#define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_12MHZ (0x24 << 10)
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#define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_15MHZ (0x1c << 10)
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#define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_16MHZ (0x1a << 10)
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#define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_19MHZ2 (0x15 << 10)
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#define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_20MHZ (0x14 << 10)
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/* PHY reset control */
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#define EXYNOS_4x12_UPHYRST 0x8
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#define EXYNOS_4x12_URSTCON_PHY0 BIT(0)
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#define EXYNOS_4x12_URSTCON_OTG_HLINK BIT(1)
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#define EXYNOS_4x12_URSTCON_OTG_PHYLINK BIT(2)
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#define EXYNOS_4x12_URSTCON_HOST_PHY BIT(3)
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/* The following bit defines are presented in the
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* order taken from the Exynos4412 reference manual.
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*
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* During experiments with the hardware and debugging
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* it was determined that the hardware behaves contrary
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* to the manual.
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*
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* The following bit values were chaned accordingly to the
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* results of real hardware experiments.
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*/
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#define EXYNOS_4x12_URSTCON_PHY1 BIT(4)
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#define EXYNOS_4x12_URSTCON_HSIC0 BIT(6)
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#define EXYNOS_4x12_URSTCON_HSIC1 BIT(5)
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#define EXYNOS_4x12_URSTCON_HOST_LINK_ALL BIT(7)
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#define EXYNOS_4x12_URSTCON_HOST_LINK_P0 BIT(10)
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#define EXYNOS_4x12_URSTCON_HOST_LINK_P1 BIT(9)
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#define EXYNOS_4x12_URSTCON_HOST_LINK_P2 BIT(8)
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/* Isolation, configured in the power management unit */
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#define EXYNOS_4x12_USB_ISOL_OFFSET 0x704
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#define EXYNOS_4x12_USB_ISOL_OTG BIT(0)
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#define EXYNOS_4x12_USB_ISOL_HSIC0_OFFSET 0x708
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#define EXYNOS_4x12_USB_ISOL_HSIC0 BIT(0)
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#define EXYNOS_4x12_USB_ISOL_HSIC1_OFFSET 0x70c
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#define EXYNOS_4x12_USB_ISOL_HSIC1 BIT(0)
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/* Mode switching SUB Device <-> Host */
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#define EXYNOS_4x12_MODE_SWITCH_OFFSET 0x21c
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#define EXYNOS_4x12_MODE_SWITCH_MASK 1
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#define EXYNOS_4x12_MODE_SWITCH_DEVICE 0
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#define EXYNOS_4x12_MODE_SWITCH_HOST 1
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enum exynos4x12_phy_id {
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EXYNOS4x12_DEVICE,
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EXYNOS4x12_HOST,
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EXYNOS4x12_HSIC0,
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EXYNOS4x12_HSIC1,
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EXYNOS4x12_NUM_PHYS,
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};
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/*
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* exynos4x12_rate_to_clk() converts the supplied clock rate to the value that
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* can be written to the phy register.
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*/
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static int exynos4x12_rate_to_clk(unsigned long rate, u32 *reg)
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{
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/* EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK */
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switch (rate) {
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case 9600 * KHZ:
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*reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6;
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break;
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case 10 * MHZ:
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*reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ;
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break;
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case 12 * MHZ:
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*reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ;
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break;
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case 19200 * KHZ:
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*reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2;
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break;
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case 20 * MHZ:
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*reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ;
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break;
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case 24 * MHZ:
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*reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_24MHZ;
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break;
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case 50 * MHZ:
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*reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_50MHZ;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static void exynos4x12_isol(struct samsung_usb2_phy_instance *inst, bool on)
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{
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struct samsung_usb2_phy_driver *drv = inst->drv;
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u32 offset;
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u32 mask;
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switch (inst->cfg->id) {
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case EXYNOS4x12_DEVICE:
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case EXYNOS4x12_HOST:
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offset = EXYNOS_4x12_USB_ISOL_OFFSET;
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mask = EXYNOS_4x12_USB_ISOL_OTG;
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break;
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case EXYNOS4x12_HSIC0:
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offset = EXYNOS_4x12_USB_ISOL_HSIC0_OFFSET;
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mask = EXYNOS_4x12_USB_ISOL_HSIC0;
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break;
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case EXYNOS4x12_HSIC1:
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offset = EXYNOS_4x12_USB_ISOL_HSIC1_OFFSET;
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mask = EXYNOS_4x12_USB_ISOL_HSIC1;
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break;
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default:
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return;
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}
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regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
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}
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static void exynos4x12_setup_clk(struct samsung_usb2_phy_instance *inst)
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{
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struct samsung_usb2_phy_driver *drv = inst->drv;
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u32 clk;
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clk = readl(drv->reg_phy + EXYNOS_4x12_UPHYCLK);
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clk &= ~EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK;
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if (drv->cfg->has_refclk_sel)
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clk = EXYNOS_3250_UPHYCLK_REFCLKSEL;
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clk |= drv->ref_reg_val << EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET;
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clk |= EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON;
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writel(clk, drv->reg_phy + EXYNOS_4x12_UPHYCLK);
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}
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static void exynos4x12_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
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{
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struct samsung_usb2_phy_driver *drv = inst->drv;
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u32 rstbits = 0;
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u32 phypwr = 0;
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u32 rst;
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u32 pwr;
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switch (inst->cfg->id) {
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case EXYNOS4x12_DEVICE:
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phypwr = EXYNOS_4x12_UPHYPWR_PHY0;
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rstbits = EXYNOS_4x12_URSTCON_PHY0;
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break;
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case EXYNOS4x12_HOST:
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phypwr = EXYNOS_4x12_UPHYPWR_PHY1;
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rstbits = EXYNOS_4x12_URSTCON_HOST_PHY |
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EXYNOS_4x12_URSTCON_PHY1 |
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EXYNOS_4x12_URSTCON_HOST_LINK_P0;
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break;
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case EXYNOS4x12_HSIC0:
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phypwr = EXYNOS_4x12_UPHYPWR_HSIC0;
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rstbits = EXYNOS_4x12_URSTCON_HSIC0 |
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EXYNOS_4x12_URSTCON_HOST_LINK_P1;
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break;
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case EXYNOS4x12_HSIC1:
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phypwr = EXYNOS_4x12_UPHYPWR_HSIC1;
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rstbits = EXYNOS_4x12_URSTCON_HSIC1 |
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EXYNOS_4x12_URSTCON_HOST_LINK_P1;
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break;
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}
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if (on) {
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pwr = readl(drv->reg_phy + EXYNOS_4x12_UPHYPWR);
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pwr &= ~phypwr;
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writel(pwr, drv->reg_phy + EXYNOS_4x12_UPHYPWR);
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rst = readl(drv->reg_phy + EXYNOS_4x12_UPHYRST);
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rst |= rstbits;
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writel(rst, drv->reg_phy + EXYNOS_4x12_UPHYRST);
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udelay(10);
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rst &= ~rstbits;
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writel(rst, drv->reg_phy + EXYNOS_4x12_UPHYRST);
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/* The following delay is necessary for the reset sequence to be
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* completed */
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udelay(80);
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} else {
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pwr = readl(drv->reg_phy + EXYNOS_4x12_UPHYPWR);
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pwr |= phypwr;
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writel(pwr, drv->reg_phy + EXYNOS_4x12_UPHYPWR);
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}
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}
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static void exynos4x12_power_on_int(struct samsung_usb2_phy_instance *inst)
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{
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if (inst->int_cnt++ > 0)
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return;
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exynos4x12_setup_clk(inst);
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exynos4x12_isol(inst, 0);
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exynos4x12_phy_pwr(inst, 1);
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}
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static int exynos4x12_power_on(struct samsung_usb2_phy_instance *inst)
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{
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struct samsung_usb2_phy_driver *drv = inst->drv;
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if (inst->ext_cnt++ > 0)
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return 0;
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if (inst->cfg->id == EXYNOS4x12_HOST) {
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regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET,
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EXYNOS_4x12_MODE_SWITCH_MASK,
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EXYNOS_4x12_MODE_SWITCH_HOST);
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exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_DEVICE]);
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}
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if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch)
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regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET,
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EXYNOS_4x12_MODE_SWITCH_MASK,
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EXYNOS_4x12_MODE_SWITCH_DEVICE);
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if (inst->cfg->id == EXYNOS4x12_HSIC0 ||
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inst->cfg->id == EXYNOS4x12_HSIC1) {
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exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_DEVICE]);
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exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_HOST]);
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}
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exynos4x12_power_on_int(inst);
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return 0;
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}
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static void exynos4x12_power_off_int(struct samsung_usb2_phy_instance *inst)
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{
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if (inst->int_cnt-- > 1)
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return;
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exynos4x12_isol(inst, 1);
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exynos4x12_phy_pwr(inst, 0);
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}
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static int exynos4x12_power_off(struct samsung_usb2_phy_instance *inst)
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{
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struct samsung_usb2_phy_driver *drv = inst->drv;
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if (inst->ext_cnt-- > 1)
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return 0;
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if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch)
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regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET,
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EXYNOS_4x12_MODE_SWITCH_MASK,
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EXYNOS_4x12_MODE_SWITCH_HOST);
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if (inst->cfg->id == EXYNOS4x12_HOST)
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exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_DEVICE]);
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if (inst->cfg->id == EXYNOS4x12_HSIC0 ||
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inst->cfg->id == EXYNOS4x12_HSIC1) {
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exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_DEVICE]);
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exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_HOST]);
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}
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exynos4x12_power_off_int(inst);
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return 0;
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}
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static const struct samsung_usb2_common_phy exynos4x12_phys[] = {
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{
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.label = "device",
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.id = EXYNOS4x12_DEVICE,
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.power_on = exynos4x12_power_on,
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.power_off = exynos4x12_power_off,
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},
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{
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.label = "host",
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.id = EXYNOS4x12_HOST,
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.power_on = exynos4x12_power_on,
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.power_off = exynos4x12_power_off,
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},
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{
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.label = "hsic0",
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.id = EXYNOS4x12_HSIC0,
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.power_on = exynos4x12_power_on,
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.power_off = exynos4x12_power_off,
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},
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{
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.label = "hsic1",
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.id = EXYNOS4x12_HSIC1,
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.power_on = exynos4x12_power_on,
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.power_off = exynos4x12_power_off,
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},
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};
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const struct samsung_usb2_phy_config exynos3250_usb2_phy_config = {
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.has_refclk_sel = 1,
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.num_phys = 1,
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.phys = exynos4x12_phys,
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.rate_to_clk = exynos4x12_rate_to_clk,
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};
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const struct samsung_usb2_phy_config exynos4x12_usb2_phy_config = {
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.has_mode_switch = 1,
|
|
.num_phys = EXYNOS4x12_NUM_PHYS,
|
|
.phys = exynos4x12_phys,
|
|
.rate_to_clk = exynos4x12_rate_to_clk,
|
|
};
|