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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-15 23:25:07 +00:00
06184ba5a3
New driver for pci phy has been added, as well as. pci driver has been changed to use kernel's generic PHY API. Add related PCI PHY bindings accordly. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
483 lines
8.7 KiB
Text
483 lines
8.7 KiB
Text
#include <dt-bindings/interrupt-controller/mips-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mediatek,mt7621-soc";
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cpus {
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cpu@0 {
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compatible = "mips,mips1004Kc";
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};
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cpu@1 {
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compatible = "mips,mips1004Kc";
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};
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};
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cpuintc: cpuintc@0 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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aliases {
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serial0 = &uartlite;
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};
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cpuclock: cpuclock@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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/* FIXME: there should be way to detect this */
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clock-frequency = <880000000>;
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};
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sysclock: sysclock@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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/* This is normally 1/4 of cpuclock */
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clock-frequency = <220000000>;
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};
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palmbus: palmbus@1E000000 {
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compatible = "palmbus";
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reg = <0x1E000000 0x100000>;
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ranges = <0x0 0x1E000000 0x0FFFFF>;
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#address-cells = <1>;
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#size-cells = <1>;
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sysc: sysc@0 {
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compatible = "mtk,mt7621-sysc";
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reg = <0x0 0x100>;
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};
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wdt: wdt@100 {
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compatible = "mtk,mt7621-wdt";
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reg = <0x100 0x100>;
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};
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gpio: gpio@600 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "mediatek,mt7621-gpio";
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gpio-controller;
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interrupt-controller;
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reg = <0x600 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
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};
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i2c: i2c@900 {
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compatible = "mediatek,mt7621-i2c";
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reg = <0x900 0x100>;
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clocks = <&sysclock>;
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resets = <&rstctrl 16>;
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reset-names = "i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c_pins>;
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};
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i2s: i2s@a00 {
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compatible = "mediatek,mt7621-i2s";
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reg = <0xa00 0x100>;
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clocks = <&sysclock>;
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resets = <&rstctrl 17>;
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reset-names = "i2s";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
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txdma-req = <2>;
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rxdma-req = <3>;
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dmas = <&gdma 4>,
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<&gdma 6>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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memc: memc@5000 {
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compatible = "mtk,mt7621-memc";
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reg = <0x300 0x100>;
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};
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cpc: cpc@1fbf0000 {
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compatible = "mtk,mt7621-cpc";
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reg = <0x1fbf0000 0x8000>;
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};
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mc: mc@1fbf8000 {
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compatible = "mtk,mt7621-mc";
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reg = <0x1fbf8000 0x8000>;
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};
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uartlite: uartlite@c00 {
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compatible = "ns16550a";
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reg = <0xc00 0x100>;
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clocks = <&sysclock>;
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clock-frequency = <50000000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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no-loopback-test;
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};
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spi0: spi@b00 {
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status = "disabled";
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compatible = "ralink,mt7621-spi";
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reg = <0xb00 0x100>;
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clocks = <&sysclock>;
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resets = <&rstctrl 18>;
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reset-names = "spi";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins>;
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};
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gdma: gdma@2800 {
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compatible = "ralink,rt3883-gdma";
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reg = <0x2800 0x800>;
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resets = <&rstctrl 14>;
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reset-names = "dma";
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interrupt-parent = <&gic>;
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interrupts = <0 13 4>;
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#dma-cells = <1>;
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#dma-channels = <16>;
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#dma-requests = <16>;
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status = "disabled";
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};
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hsdma: hsdma@7000 {
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compatible = "mediatek,mt7621-hsdma";
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reg = <0x7000 0x1000>;
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resets = <&rstctrl 5>;
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reset-names = "hsdma";
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interrupt-parent = <&gic>;
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interrupts = <0 11 4>;
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#dma-cells = <1>;
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#dma-channels = <1>;
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#dma-requests = <1>;
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status = "disabled";
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};
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};
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pinctrl: pinctrl {
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compatible = "ralink,rt2880-pinmux";
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinctrl0 {
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};
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i2c_pins: i2c0 {
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i2c0 {
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groups = "i2c";
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function = "i2c";
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};
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};
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spi_pins: spi0 {
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spi0 {
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groups = "spi";
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function = "spi";
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};
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};
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uart1_pins: uart1 {
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uart1 {
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groups = "uart1";
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function = "uart1";
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};
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};
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uart2_pins: uart2 {
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uart2 {
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groups = "uart2";
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function = "uart2";
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};
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};
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uart3_pins: uart3 {
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uart3 {
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groups = "uart3";
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function = "uart3";
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};
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};
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rgmii1_pins: rgmii1 {
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rgmii1 {
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groups = "rgmii1";
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function = "rgmii1";
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};
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};
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rgmii2_pins: rgmii2 {
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rgmii2 {
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groups = "rgmii2";
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function = "rgmii2";
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};
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};
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mdio_pins: mdio0 {
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mdio0 {
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groups = "mdio";
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function = "mdio";
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};
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};
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pcie_pins: pcie0 {
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pcie0 {
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groups = "pcie";
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function = "pcie rst";
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};
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};
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nand_pins: nand0 {
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spi-nand {
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groups = "spi";
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function = "nand1";
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};
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sdhci-nand {
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groups = "sdhci";
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function = "nand2";
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};
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};
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sdhci_pins: sdhci0 {
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sdhci0 {
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groups = "sdhci";
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function = "sdhci";
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};
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};
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};
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rstctrl: rstctrl {
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compatible = "ralink,rt2880-reset";
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#reset-cells = <1>;
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};
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clkctrl: clkctrl {
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compatible = "ralink,rt2880-clock";
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#clock-cells = <1>;
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};
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sdhci: sdhci@1E130000 {
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status = "disabled";
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compatible = "ralink,mt7620-sdhci";
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reg = <0x1E130000 0x4000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
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};
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xhci: xhci@1E1C0000 {
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status = "okay";
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compatible = "mediatek,mt8173-xhci";
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reg = <0x1e1c0000 0x1000
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0x1e1d0700 0x0100>;
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reg-names = "mac", "ippc";
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clocks = <&sysclock>;
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clock-names = "sys_ck";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
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};
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gic: interrupt-controller@1fbc0000 {
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compatible = "mti,gic";
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reg = <0x1fbc0000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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mti,reserved-cpu-vectors = <7>;
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
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clocks = <&cpuclock>;
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};
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};
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nand: nand@1e003000 {
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status = "disabled";
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compatible = "mtk,mt7621-nand";
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bank-width = <2>;
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reg = <0x1e003000 0x800
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0x1e003800 0x800>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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ethsys: syscon@1e000000 {
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compatible = "mediatek,mt7621-ethsys",
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"syscon";
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reg = <0x1e000000 0x1000>;
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#clock-cells = <1>;
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};
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ethernet: ethernet@1e100000 {
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compatible = "mediatek,mt7621-eth";
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reg = <0x1e100000 0x10000>;
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clocks = <&sysclock>;
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clock-names = "ethif";
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#address-cells = <1>;
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#size-cells = <0>;
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resets = <&rstctrl 6 &rstctrl 23>;
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reset-names = "fe", "eth";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
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mediatek,ethsys = <ðsys>;
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mediatek,switch = <&gsw>;
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mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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phy1f: ethernet-phy@1f {
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reg = <0x1f>;
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phy-mode = "rgmii";
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};
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};
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};
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gsw: gsw@1e110000 {
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compatible = "mediatek,mt7621-gsw";
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reg = <0x1e110000 0x8000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
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};
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pcie: pcie@1e140000 {
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compatible = "mediatek,mt7621-pci";
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reg = <0x1e140000 0x100 /* host-pci bridge registers */
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0x1e142000 0x100 /* pcie port 0 RC control registers */
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0x1e143000 0x100 /* pcie port 1 RC control registers */
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0x1e144000 0x100>; /* pcie port 2 RC control registers */
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#address-cells = <3>;
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#size-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_pins>;
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device_type = "pci";
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bus-range = <0 255>;
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ranges = <
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0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
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0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
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>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xF0000 0 0 1>;
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interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
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<0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
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<0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
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reset-names = "pcie0", "pcie1", "pcie2";
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clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
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clock-names = "pcie0", "pcie1", "pcie2";
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phys = <&pcie0_port>, <&pcie1_port>, <&pcie2_port>;
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phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
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pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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bus-range = <0x00 0xff>;
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};
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pcie@1,0 {
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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bus-range = <0x00 0xff>;
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};
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pcie@2,0 {
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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bus-range = <0x00 0xff>;
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};
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};
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pcie0_phy: pcie-phy@1a149000 {
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compatible = "mediatek,mt7621-pci-phy";
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reg = <0x1a149000 0x0700>;
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#address-cells = <1>;
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#size-cells = <0>;
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pcie0_port: pcie-phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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};
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pcie1_port: pcie-phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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};
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};
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pcie1_phy: pcie-phy@1a14a000 {
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compatible = "mediatek,mt7621-pci-phy";
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reg = <0x1a14a000 0x0700>;
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#address-cells = <1>;
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#size-cells = <0>;
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pcie2_port: pcie-phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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};
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};
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};
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