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![Thomas Gleixner](/assets/img/avatar_default.png)
Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
474 lines
13 KiB
C
474 lines
13 KiB
C
/*
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* GPIO controller driver for Intel Lynxpoint PCH chipset>
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* Copyright (c) 2012, Intel Corporation.
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*
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* Author: Mathias Nyman <mathias.nyman@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/acpi.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/io.h>
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/* LynxPoint chipset has support for 94 gpio pins */
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#define LP_NUM_GPIO 94
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/* Bitmapped register offsets */
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#define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
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#define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
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#define LP_INT_STAT 0x80
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#define LP_INT_ENABLE 0x90
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/* Each pin has two 32 bit config registers, starting at 0x100 */
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#define LP_CONFIG1 0x100
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#define LP_CONFIG2 0x104
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/* LP_CONFIG1 reg bits */
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#define OUT_LVL_BIT BIT(31)
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#define IN_LVL_BIT BIT(30)
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#define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */
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#define INT_INV_BIT BIT(3) /* Invert interrupt triggering */
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#define DIR_BIT BIT(2) /* 0: Output, 1: Input */
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#define USE_SEL_BIT BIT(0) /* 0: Native, 1: GPIO */
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/* LP_CONFIG2 reg bits */
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#define GPINDIS_BIT BIT(2) /* disable input sensing */
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#define GPIWP_BIT (BIT(0) | BIT(1)) /* weak pull options */
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struct lp_gpio {
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struct gpio_chip chip;
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struct platform_device *pdev;
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spinlock_t lock;
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unsigned long reg_base;
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};
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/*
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* Lynxpoint gpios are controlled through both bitmapped registers and
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* per gpio specific registers. The bitmapped registers are in chunks of
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* 3 x 32bit registers to cover all 94 gpios
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*
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* per gpio specific registers consist of two 32bit registers per gpio
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* (LP_CONFIG1 and LP_CONFIG2), with 94 gpios there's a total of
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* 188 config registers.
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*
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* A simplified view of the register layout look like this:
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*
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* LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
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* LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
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* LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
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* ...
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* LP_INT_ENABLE[31:0] ...
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* LP_INT_ENABLE[63:31] ...
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* LP_INT_ENABLE[94:64] ...
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* LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
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* LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
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* LP1_CONFIG1 (gpio 1) config1 reg for gpio 1
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* LP1_CONFIG2 (gpio 1) config2 reg for gpio 1
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* LP2_CONFIG1 (gpio 2) ...
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* LP2_CONFIG2 (gpio 2) ...
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* ...
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* LP94_CONFIG1 (gpio 94) ...
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* LP94_CONFIG2 (gpio 94) ...
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*/
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static unsigned long lp_gpio_reg(struct gpio_chip *chip, unsigned offset,
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int reg)
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{
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struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
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int reg_offset;
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if (reg == LP_CONFIG1 || reg == LP_CONFIG2)
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/* per gpio specific config registers */
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reg_offset = offset * 8;
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else
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/* bitmapped registers */
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reg_offset = (offset / 32) * 4;
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return lg->reg_base + reg + reg_offset;
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}
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static int lp_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
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unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
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unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
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unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED);
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pm_runtime_get(&lg->pdev->dev); /* should we put if failed */
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/* Fail if BIOS reserved pin for ACPI use */
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if (!(inl(acpi_use) & BIT(offset % 32))) {
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dev_err(&lg->pdev->dev, "gpio %d reserved for ACPI\n", offset);
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return -EBUSY;
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}
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/* Fail if pin is in alternate function mode (not GPIO mode) */
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if (!(inl(reg) & USE_SEL_BIT))
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return -ENODEV;
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/* enable input sensing */
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outl(inl(conf2) & ~GPINDIS_BIT, conf2);
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return 0;
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}
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static void lp_gpio_free(struct gpio_chip *chip, unsigned offset)
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{
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struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
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unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
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/* disable input sensing */
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outl(inl(conf2) | GPINDIS_BIT, conf2);
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pm_runtime_put(&lg->pdev->dev);
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}
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static int lp_irq_type(struct irq_data *d, unsigned type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct lp_gpio *lg = container_of(gc, struct lp_gpio, chip);
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u32 hwirq = irqd_to_hwirq(d);
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unsigned long flags;
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u32 value;
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unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
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if (hwirq >= lg->chip.ngpio)
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return -EINVAL;
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spin_lock_irqsave(&lg->lock, flags);
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value = inl(reg);
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/* set both TRIG_SEL and INV bits to 0 for rising edge */
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if (type & IRQ_TYPE_EDGE_RISING)
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value &= ~(TRIG_SEL_BIT | INT_INV_BIT);
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/* TRIG_SEL bit 0, INV bit 1 for falling edge */
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if (type & IRQ_TYPE_EDGE_FALLING)
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value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;
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/* TRIG_SEL bit 1, INV bit 0 for level low */
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if (type & IRQ_TYPE_LEVEL_LOW)
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value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;
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/* TRIG_SEL bit 1, INV bit 1 for level high */
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if (type & IRQ_TYPE_LEVEL_HIGH)
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value |= TRIG_SEL_BIT | INT_INV_BIT;
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outl(value, reg);
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spin_unlock_irqrestore(&lg->lock, flags);
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return 0;
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}
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static int lp_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
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return !!(inl(reg) & IN_LVL_BIT);
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}
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static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
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unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
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unsigned long flags;
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spin_lock_irqsave(&lg->lock, flags);
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if (value)
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outl(inl(reg) | OUT_LVL_BIT, reg);
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else
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outl(inl(reg) & ~OUT_LVL_BIT, reg);
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spin_unlock_irqrestore(&lg->lock, flags);
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}
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static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
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unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
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unsigned long flags;
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spin_lock_irqsave(&lg->lock, flags);
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outl(inl(reg) | DIR_BIT, reg);
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spin_unlock_irqrestore(&lg->lock, flags);
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return 0;
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}
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static int lp_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
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unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
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unsigned long flags;
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lp_gpio_set(chip, offset, value);
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spin_lock_irqsave(&lg->lock, flags);
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outl(inl(reg) & ~DIR_BIT, reg);
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spin_unlock_irqrestore(&lg->lock, flags);
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return 0;
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}
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static void lp_gpio_irq_handler(struct irq_desc *desc)
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{
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struct irq_data *data = irq_desc_get_irq_data(desc);
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct lp_gpio *lg = container_of(gc, struct lp_gpio, chip);
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struct irq_chip *chip = irq_data_get_irq_chip(data);
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u32 base, pin, mask;
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unsigned long reg, ena, pending;
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/* check from GPIO controller which pin triggered the interrupt */
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for (base = 0; base < lg->chip.ngpio; base += 32) {
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reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
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ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
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while ((pending = (inl(reg) & inl(ena)))) {
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unsigned irq;
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pin = __ffs(pending);
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mask = BIT(pin);
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/* Clear before handling so we don't lose an edge */
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outl(mask, reg);
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irq = irq_find_mapping(lg->chip.irqdomain, base + pin);
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generic_handle_irq(irq);
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}
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}
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chip->irq_eoi(data);
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}
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static void lp_irq_unmask(struct irq_data *d)
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{
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}
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static void lp_irq_mask(struct irq_data *d)
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{
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}
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static void lp_irq_enable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct lp_gpio *lg = container_of(gc, struct lp_gpio, chip);
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u32 hwirq = irqd_to_hwirq(d);
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unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
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unsigned long flags;
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spin_lock_irqsave(&lg->lock, flags);
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outl(inl(reg) | BIT(hwirq % 32), reg);
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spin_unlock_irqrestore(&lg->lock, flags);
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}
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static void lp_irq_disable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct lp_gpio *lg = container_of(gc, struct lp_gpio, chip);
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u32 hwirq = irqd_to_hwirq(d);
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unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
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unsigned long flags;
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spin_lock_irqsave(&lg->lock, flags);
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outl(inl(reg) & ~BIT(hwirq % 32), reg);
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spin_unlock_irqrestore(&lg->lock, flags);
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}
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static struct irq_chip lp_irqchip = {
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.name = "LP-GPIO",
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.irq_mask = lp_irq_mask,
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.irq_unmask = lp_irq_unmask,
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.irq_enable = lp_irq_enable,
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.irq_disable = lp_irq_disable,
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.irq_set_type = lp_irq_type,
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.flags = IRQCHIP_SKIP_SET_WAKE,
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};
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static void lp_gpio_irq_init_hw(struct lp_gpio *lg)
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{
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unsigned long reg;
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unsigned base;
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for (base = 0; base < lg->chip.ngpio; base += 32) {
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/* disable gpio pin interrupts */
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reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
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outl(0, reg);
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/* Clear interrupt status register */
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reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
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outl(0xffffffff, reg);
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}
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}
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static int lp_gpio_probe(struct platform_device *pdev)
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{
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struct lp_gpio *lg;
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struct gpio_chip *gc;
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struct resource *io_rc, *irq_rc;
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struct device *dev = &pdev->dev;
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unsigned long reg_len;
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int ret = -ENODEV;
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lg = devm_kzalloc(dev, sizeof(struct lp_gpio), GFP_KERNEL);
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if (!lg)
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return -ENOMEM;
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lg->pdev = pdev;
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platform_set_drvdata(pdev, lg);
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io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
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irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (!io_rc) {
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dev_err(dev, "missing IO resources\n");
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return -EINVAL;
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}
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lg->reg_base = io_rc->start;
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reg_len = resource_size(io_rc);
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if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) {
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dev_err(dev, "failed requesting IO region 0x%x\n",
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(unsigned int)lg->reg_base);
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return -EBUSY;
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}
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spin_lock_init(&lg->lock);
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gc = &lg->chip;
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gc->label = dev_name(dev);
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gc->owner = THIS_MODULE;
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gc->request = lp_gpio_request;
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gc->free = lp_gpio_free;
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gc->direction_input = lp_gpio_direction_input;
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gc->direction_output = lp_gpio_direction_output;
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gc->get = lp_gpio_get;
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gc->set = lp_gpio_set;
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gc->base = -1;
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gc->ngpio = LP_NUM_GPIO;
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gc->can_sleep = false;
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gc->dev = dev;
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ret = gpiochip_add(gc);
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if (ret) {
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dev_err(dev, "failed adding lp-gpio chip\n");
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return ret;
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}
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/* set up interrupts */
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if (irq_rc && irq_rc->start) {
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lp_gpio_irq_init_hw(lg);
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ret = gpiochip_irqchip_add(gc, &lp_irqchip, 0,
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handle_simple_irq, IRQ_TYPE_NONE);
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if (ret) {
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dev_err(dev, "failed to add irqchip\n");
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gpiochip_remove(gc);
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return ret;
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}
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gpiochip_set_chained_irqchip(gc, &lp_irqchip,
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(unsigned)irq_rc->start,
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lp_gpio_irq_handler);
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}
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pm_runtime_enable(dev);
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return 0;
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}
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static int lp_gpio_runtime_suspend(struct device *dev)
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{
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return 0;
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}
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static int lp_gpio_runtime_resume(struct device *dev)
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{
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return 0;
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}
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static int lp_gpio_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct lp_gpio *lg = platform_get_drvdata(pdev);
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unsigned long reg;
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int i;
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/* on some hardware suspend clears input sensing, re-enable it here */
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for (i = 0; i < lg->chip.ngpio; i++) {
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if (gpiochip_is_requested(&lg->chip, i) != NULL) {
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reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2);
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outl(inl(reg) & ~GPINDIS_BIT, reg);
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}
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}
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return 0;
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}
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static const struct dev_pm_ops lp_gpio_pm_ops = {
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.runtime_suspend = lp_gpio_runtime_suspend,
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.runtime_resume = lp_gpio_runtime_resume,
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.resume = lp_gpio_resume,
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};
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static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
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{ "INT33C7", 0 },
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{ "INT3437", 0 },
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{ }
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};
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MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
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static int lp_gpio_remove(struct platform_device *pdev)
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{
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struct lp_gpio *lg = platform_get_drvdata(pdev);
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pm_runtime_disable(&pdev->dev);
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gpiochip_remove(&lg->chip);
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return 0;
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}
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static struct platform_driver lp_gpio_driver = {
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.probe = lp_gpio_probe,
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.remove = lp_gpio_remove,
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.driver = {
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.name = "lp_gpio",
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.pm = &lp_gpio_pm_ops,
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.acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match),
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},
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};
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static int __init lp_gpio_init(void)
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{
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return platform_driver_register(&lp_gpio_driver);
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}
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static void __exit lp_gpio_exit(void)
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{
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platform_driver_unregister(&lp_gpio_driver);
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}
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subsys_initcall(lp_gpio_init);
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module_exit(lp_gpio_exit);
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MODULE_AUTHOR("Mathias Nyman (Intel)");
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MODULE_DESCRIPTION("GPIO interface for Intel Lynxpoint");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:lp_gpio");
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