384 lines
10 KiB
C
384 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Regents of the University of California
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* Copyright (c) 2020 Western Digital Corporation or its affiliates.
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*/
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#ifndef _ASM_RISCV_SBI_H
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#define _ASM_RISCV_SBI_H
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#include <linux/types.h>
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#include <linux/cpumask.h>
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#ifdef CONFIG_RISCV_SBI
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enum sbi_ext_id {
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#ifdef CONFIG_RISCV_SBI_V01
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SBI_EXT_0_1_SET_TIMER = 0x0,
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SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
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SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
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SBI_EXT_0_1_CLEAR_IPI = 0x3,
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SBI_EXT_0_1_SEND_IPI = 0x4,
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SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
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SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
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SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
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SBI_EXT_0_1_SHUTDOWN = 0x8,
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#endif
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SBI_EXT_BASE = 0x10,
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SBI_EXT_TIME = 0x54494D45,
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SBI_EXT_IPI = 0x735049,
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SBI_EXT_RFENCE = 0x52464E43,
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SBI_EXT_HSM = 0x48534D,
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SBI_EXT_SRST = 0x53525354,
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SBI_EXT_SUSP = 0x53555350,
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SBI_EXT_PMU = 0x504D55,
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SBI_EXT_DBCN = 0x4442434E,
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SBI_EXT_STA = 0x535441,
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/* Experimentals extensions must lie within this range */
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SBI_EXT_EXPERIMENTAL_START = 0x08000000,
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SBI_EXT_EXPERIMENTAL_END = 0x08FFFFFF,
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/* Vendor extensions must lie within this range */
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SBI_EXT_VENDOR_START = 0x09000000,
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SBI_EXT_VENDOR_END = 0x09FFFFFF,
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};
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enum sbi_ext_base_fid {
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SBI_EXT_BASE_GET_SPEC_VERSION = 0,
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SBI_EXT_BASE_GET_IMP_ID,
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SBI_EXT_BASE_GET_IMP_VERSION,
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SBI_EXT_BASE_PROBE_EXT,
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SBI_EXT_BASE_GET_MVENDORID,
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SBI_EXT_BASE_GET_MARCHID,
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SBI_EXT_BASE_GET_MIMPID,
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};
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enum sbi_ext_time_fid {
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SBI_EXT_TIME_SET_TIMER = 0,
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};
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enum sbi_ext_ipi_fid {
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SBI_EXT_IPI_SEND_IPI = 0,
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};
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enum sbi_ext_rfence_fid {
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SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
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SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
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SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
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SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
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SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
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SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
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SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
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};
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enum sbi_ext_hsm_fid {
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SBI_EXT_HSM_HART_START = 0,
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SBI_EXT_HSM_HART_STOP,
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SBI_EXT_HSM_HART_STATUS,
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SBI_EXT_HSM_HART_SUSPEND,
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};
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enum sbi_hsm_hart_state {
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SBI_HSM_STATE_STARTED = 0,
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SBI_HSM_STATE_STOPPED,
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SBI_HSM_STATE_START_PENDING,
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SBI_HSM_STATE_STOP_PENDING,
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SBI_HSM_STATE_SUSPENDED,
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SBI_HSM_STATE_SUSPEND_PENDING,
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SBI_HSM_STATE_RESUME_PENDING,
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};
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#define SBI_HSM_SUSP_BASE_MASK 0x7fffffff
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#define SBI_HSM_SUSP_NON_RET_BIT 0x80000000
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#define SBI_HSM_SUSP_PLAT_BASE 0x10000000
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#define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000
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#define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE
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#define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK
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#define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT
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#define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \
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SBI_HSM_SUSP_PLAT_BASE)
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#define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \
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SBI_HSM_SUSP_BASE_MASK)
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enum sbi_ext_srst_fid {
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SBI_EXT_SRST_RESET = 0,
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};
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enum sbi_srst_reset_type {
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SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
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SBI_SRST_RESET_TYPE_COLD_REBOOT,
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SBI_SRST_RESET_TYPE_WARM_REBOOT,
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};
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enum sbi_srst_reset_reason {
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SBI_SRST_RESET_REASON_NONE = 0,
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SBI_SRST_RESET_REASON_SYS_FAILURE,
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};
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enum sbi_ext_susp_fid {
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SBI_EXT_SUSP_SYSTEM_SUSPEND = 0,
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};
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enum sbi_ext_susp_sleep_type {
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SBI_SUSP_SLEEP_TYPE_SUSPEND_TO_RAM = 0,
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};
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enum sbi_ext_pmu_fid {
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SBI_EXT_PMU_NUM_COUNTERS = 0,
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SBI_EXT_PMU_COUNTER_GET_INFO,
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SBI_EXT_PMU_COUNTER_CFG_MATCH,
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SBI_EXT_PMU_COUNTER_START,
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SBI_EXT_PMU_COUNTER_STOP,
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SBI_EXT_PMU_COUNTER_FW_READ,
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};
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union sbi_pmu_ctr_info {
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unsigned long value;
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struct {
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unsigned long csr:12;
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unsigned long width:6;
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#if __riscv_xlen == 32
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unsigned long reserved:13;
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#else
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unsigned long reserved:45;
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#endif
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unsigned long type:1;
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};
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};
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#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0)
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#define RISCV_PMU_RAW_EVENT_IDX 0x20000
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/** General pmu event codes specified in SBI PMU extension */
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enum sbi_pmu_hw_generic_events_t {
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SBI_PMU_HW_NO_EVENT = 0,
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SBI_PMU_HW_CPU_CYCLES = 1,
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SBI_PMU_HW_INSTRUCTIONS = 2,
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SBI_PMU_HW_CACHE_REFERENCES = 3,
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SBI_PMU_HW_CACHE_MISSES = 4,
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SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5,
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SBI_PMU_HW_BRANCH_MISSES = 6,
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SBI_PMU_HW_BUS_CYCLES = 7,
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SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8,
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SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9,
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SBI_PMU_HW_REF_CPU_CYCLES = 10,
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SBI_PMU_HW_GENERAL_MAX,
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};
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/**
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* Special "firmware" events provided by the firmware, even if the hardware
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* does not support performance events. These events are encoded as a raw
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* event type in Linux kernel perf framework.
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*/
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enum sbi_pmu_fw_generic_events_t {
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SBI_PMU_FW_MISALIGNED_LOAD = 0,
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SBI_PMU_FW_MISALIGNED_STORE = 1,
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SBI_PMU_FW_ACCESS_LOAD = 2,
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SBI_PMU_FW_ACCESS_STORE = 3,
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SBI_PMU_FW_ILLEGAL_INSN = 4,
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SBI_PMU_FW_SET_TIMER = 5,
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SBI_PMU_FW_IPI_SENT = 6,
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SBI_PMU_FW_IPI_RCVD = 7,
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SBI_PMU_FW_FENCE_I_SENT = 8,
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SBI_PMU_FW_FENCE_I_RCVD = 9,
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SBI_PMU_FW_SFENCE_VMA_SENT = 10,
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SBI_PMU_FW_SFENCE_VMA_RCVD = 11,
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SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12,
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SBI_PMU_FW_SFENCE_VMA_ASID_RCVD = 13,
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SBI_PMU_FW_HFENCE_GVMA_SENT = 14,
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SBI_PMU_FW_HFENCE_GVMA_RCVD = 15,
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SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16,
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SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17,
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SBI_PMU_FW_HFENCE_VVMA_SENT = 18,
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SBI_PMU_FW_HFENCE_VVMA_RCVD = 19,
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SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20,
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SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21,
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SBI_PMU_FW_MAX,
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};
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/* SBI PMU event types */
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enum sbi_pmu_event_type {
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SBI_PMU_EVENT_TYPE_HW = 0x0,
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SBI_PMU_EVENT_TYPE_CACHE = 0x1,
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SBI_PMU_EVENT_TYPE_RAW = 0x2,
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SBI_PMU_EVENT_TYPE_FW = 0xf,
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};
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/* SBI PMU event types */
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enum sbi_pmu_ctr_type {
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SBI_PMU_CTR_TYPE_HW = 0x0,
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SBI_PMU_CTR_TYPE_FW,
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};
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/* Helper macros to decode event idx */
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#define SBI_PMU_EVENT_IDX_OFFSET 20
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#define SBI_PMU_EVENT_IDX_MASK 0xFFFFF
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#define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF
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#define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000
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#define SBI_PMU_EVENT_RAW_IDX 0x20000
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#define SBI_PMU_FIXED_CTR_MASK 0x07
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#define SBI_PMU_EVENT_CACHE_ID_CODE_MASK 0xFFF8
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#define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06
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#define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01
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#define SBI_PMU_EVENT_CACHE_ID_SHIFT 3
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#define SBI_PMU_EVENT_CACHE_OP_SHIFT 1
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#define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF
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/* Flags defined for config matching function */
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#define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0)
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#define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1)
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#define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2)
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#define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3)
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#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4)
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#define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5)
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#define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6)
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#define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7)
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/* Flags defined for counter start function */
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#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0)
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/* Flags defined for counter stop function */
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#define SBI_PMU_STOP_FLAG_RESET (1 << 0)
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enum sbi_ext_dbcn_fid {
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SBI_EXT_DBCN_CONSOLE_WRITE = 0,
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SBI_EXT_DBCN_CONSOLE_READ = 1,
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SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2,
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};
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/* SBI STA (steal-time accounting) extension */
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enum sbi_ext_sta_fid {
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SBI_EXT_STA_STEAL_TIME_SET_SHMEM = 0,
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};
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struct sbi_sta_struct {
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__le32 sequence;
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__le32 flags;
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__le64 steal;
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u8 preempted;
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u8 pad[47];
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} __packed;
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#define SBI_STA_SHMEM_DISABLE -1
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/* SBI spec version fields */
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#define SBI_SPEC_VERSION_DEFAULT 0x1
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#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
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#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
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#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
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/* SBI return error codes */
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#define SBI_SUCCESS 0
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#define SBI_ERR_FAILURE -1
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#define SBI_ERR_NOT_SUPPORTED -2
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#define SBI_ERR_INVALID_PARAM -3
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#define SBI_ERR_DENIED -4
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#define SBI_ERR_INVALID_ADDRESS -5
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#define SBI_ERR_ALREADY_AVAILABLE -6
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#define SBI_ERR_ALREADY_STARTED -7
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#define SBI_ERR_ALREADY_STOPPED -8
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extern unsigned long sbi_spec_version;
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struct sbiret {
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long error;
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long value;
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};
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void sbi_init(void);
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struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
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unsigned long arg1, unsigned long arg2,
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unsigned long arg3, unsigned long arg4,
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unsigned long arg5);
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#ifdef CONFIG_RISCV_SBI_V01
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void sbi_console_putchar(int ch);
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int sbi_console_getchar(void);
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#else
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static inline void sbi_console_putchar(int ch) { }
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static inline int sbi_console_getchar(void) { return -ENOENT; }
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#endif
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long sbi_get_mvendorid(void);
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long sbi_get_marchid(void);
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long sbi_get_mimpid(void);
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void sbi_set_timer(uint64_t stime_value);
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void sbi_shutdown(void);
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void sbi_send_ipi(unsigned int cpu);
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int sbi_remote_fence_i(const struct cpumask *cpu_mask);
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int sbi_remote_sfence_vma_asid(const struct cpumask *cpu_mask,
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unsigned long start,
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unsigned long size,
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unsigned long asid);
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int sbi_remote_hfence_gvma(const struct cpumask *cpu_mask,
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unsigned long start,
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unsigned long size);
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int sbi_remote_hfence_gvma_vmid(const struct cpumask *cpu_mask,
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unsigned long start,
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unsigned long size,
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unsigned long vmid);
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int sbi_remote_hfence_vvma(const struct cpumask *cpu_mask,
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unsigned long start,
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unsigned long size);
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int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask,
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unsigned long start,
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unsigned long size,
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unsigned long asid);
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long sbi_probe_extension(int ext);
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/* Check if current SBI specification version is 0.1 or not */
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static inline int sbi_spec_is_0_1(void)
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{
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return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0;
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}
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/* Get the major version of SBI */
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static inline unsigned long sbi_major_version(void)
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{
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return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_SHIFT) &
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SBI_SPEC_VERSION_MAJOR_MASK;
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}
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/* Get the minor version of SBI */
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static inline unsigned long sbi_minor_version(void)
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{
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return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK;
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}
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/* Make SBI version */
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static inline unsigned long sbi_mk_version(unsigned long major,
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unsigned long minor)
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{
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return ((major & SBI_SPEC_VERSION_MAJOR_MASK) <<
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SBI_SPEC_VERSION_MAJOR_SHIFT) | minor;
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}
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int sbi_err_map_linux_errno(int err);
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extern bool sbi_debug_console_available;
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int sbi_debug_console_write(const char *bytes, unsigned int num_bytes);
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int sbi_debug_console_read(char *bytes, unsigned int num_bytes);
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#else /* CONFIG_RISCV_SBI */
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static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1; }
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static inline void sbi_init(void) {}
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#endif /* CONFIG_RISCV_SBI */
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unsigned long riscv_cached_mvendorid(unsigned int cpu_id);
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unsigned long riscv_cached_marchid(unsigned int cpu_id);
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unsigned long riscv_cached_mimpid(unsigned int cpu_id);
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#if IS_ENABLED(CONFIG_SMP) && IS_ENABLED(CONFIG_RISCV_SBI)
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void sbi_ipi_init(void);
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#else
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static inline void sbi_ipi_init(void) { }
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#endif
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#endif /* _ASM_RISCV_SBI_H */
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