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The CVB table contains calibration data for the CPU DFLL based on process characterization. The regulator step and offset parameters depend on the regulator supplying vdd-cpu, not on the specific Tegra SKU. When using a PWM controlled regulator, the voltage step and offset are determined by the regulator type in use. This is specified in DT. When using an I2C controlled regulator, we can retrieve them from CPU regulator Then pass this information to the CVB table calculation function. Based on the work done of "Peter De Schrijver <pdeschrijver@nvidia.com>" and "Alex Frid <afrid@nvidia.com>". Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
54 lines
1.9 KiB
C
54 lines
1.9 KiB
C
/*
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* clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver
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* Copyright (C) 2013-2019 NVIDIA Corporation. All rights reserved.
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*
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* Aleksandr Frid <afrid@nvidia.com>
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* Paul Walmsley <pwalmsley@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __DRIVERS_CLK_TEGRA_CLK_DFLL_H
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#define __DRIVERS_CLK_TEGRA_CLK_DFLL_H
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/types.h>
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#include "cvb.h"
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/**
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* struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
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* @dev: struct device * that holds the OPP table for the DFLL
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* @max_freq: maximum frequency supported on this SoC
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* @cvb: CPU frequency table for this SoC
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* @alignment: parameters of the regulator step and offset
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* @init_clock_trimmers: callback to initialize clock trimmers
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* @set_clock_trimmers_high: callback to tune clock trimmers for high voltage
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* @set_clock_trimmers_low: callback to tune clock trimmers for low voltage
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*/
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struct tegra_dfll_soc_data {
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struct device *dev;
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unsigned long max_freq;
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const struct cvb_table *cvb;
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struct rail_alignment alignment;
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void (*init_clock_trimmers)(void);
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void (*set_clock_trimmers_high)(void);
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void (*set_clock_trimmers_low)(void);
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};
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int tegra_dfll_register(struct platform_device *pdev,
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struct tegra_dfll_soc_data *soc);
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struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev);
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int tegra_dfll_runtime_suspend(struct device *dev);
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int tegra_dfll_runtime_resume(struct device *dev);
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#endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */
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