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e5f809171a
By default DISPC asserts hsync and vsync sequentially, i.e. there's first hsync and that is immediately followed by vsync. This is the only available behaviour on OMAP2/3, and default behaviour on OMAP4+. OMAP4+ has ALIGN bit in POL_FREQ register, which makes DISPC assert both syncs at the same time. It has been observed that some panels don't like sequential syncs (AM5 EVM's panel). After studying the datasheets for multiple panels and encoders, and MIPI DPI spec, it looks like there is no standard way to handle this. Sometimes the datasheets don't mention the required syncs behaviour at all, sometimes the datasheets have images that hint towards simultaneous syncs, and sometimes it is explicitly mentioned that simultaneous syncs are needed. No panels or encoders requiring sequential sync was found. It thus seems to be safe to default to simultaneous syncs when the ALIGN bit is available. This fixed AM5 EVM's panel, and no side effects have been observed on other panels or encoders. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
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| backlight | ||
| console | ||
| fbdev | ||
| logo | ||
| display_timing.c | ||
| hdmi.c | ||
| Kconfig | ||
| Makefile | ||
| of_display_timing.c | ||
| of_videomode.c | ||
| vgastate.c | ||
| videomode.c | ||