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52fa82c21f
Add a helper to decode kernel instructions; there's no point in endlessly repeating those last two arguments. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20210326151259.379242587@infradead.org
276 lines
7.7 KiB
C
276 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _ASM_X86_INSN_H
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#define _ASM_X86_INSN_H
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/*
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* x86 instruction analysis
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*
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* Copyright (C) IBM Corporation, 2009
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*/
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#include <asm/byteorder.h>
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/* insn_attr_t is defined in inat.h */
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#include <asm/inat.h> /* __ignore_sync_check__ */
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#if defined(__BYTE_ORDER) ? __BYTE_ORDER == __LITTLE_ENDIAN : defined(__LITTLE_ENDIAN)
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struct insn_field {
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union {
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insn_value_t value;
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insn_byte_t bytes[4];
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};
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/* !0 if we've run insn_get_xxx() for this field */
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unsigned char got;
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unsigned char nbytes;
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};
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static inline void insn_field_set(struct insn_field *p, insn_value_t v,
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unsigned char n)
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{
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p->value = v;
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p->nbytes = n;
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}
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static inline void insn_set_byte(struct insn_field *p, unsigned char n,
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insn_byte_t v)
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{
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p->bytes[n] = v;
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}
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#else
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struct insn_field {
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insn_value_t value;
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union {
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insn_value_t little;
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insn_byte_t bytes[4];
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};
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/* !0 if we've run insn_get_xxx() for this field */
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unsigned char got;
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unsigned char nbytes;
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};
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static inline void insn_field_set(struct insn_field *p, insn_value_t v,
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unsigned char n)
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{
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p->value = v;
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p->little = __cpu_to_le32(v);
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p->nbytes = n;
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}
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static inline void insn_set_byte(struct insn_field *p, unsigned char n,
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insn_byte_t v)
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{
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p->bytes[n] = v;
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p->value = __le32_to_cpu(p->little);
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}
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#endif
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struct insn {
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struct insn_field prefixes; /*
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* Prefixes
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* prefixes.bytes[3]: last prefix
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*/
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struct insn_field rex_prefix; /* REX prefix */
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struct insn_field vex_prefix; /* VEX prefix */
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struct insn_field opcode; /*
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* opcode.bytes[0]: opcode1
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* opcode.bytes[1]: opcode2
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* opcode.bytes[2]: opcode3
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*/
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struct insn_field modrm;
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struct insn_field sib;
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struct insn_field displacement;
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union {
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struct insn_field immediate;
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struct insn_field moffset1; /* for 64bit MOV */
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struct insn_field immediate1; /* for 64bit imm or off16/32 */
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};
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union {
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struct insn_field moffset2; /* for 64bit MOV */
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struct insn_field immediate2; /* for 64bit imm or seg16 */
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};
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int emulate_prefix_size;
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insn_attr_t attr;
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unsigned char opnd_bytes;
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unsigned char addr_bytes;
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unsigned char length;
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unsigned char x86_64;
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const insn_byte_t *kaddr; /* kernel address of insn to analyze */
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const insn_byte_t *end_kaddr; /* kernel address of last insn in buffer */
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const insn_byte_t *next_byte;
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};
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#define MAX_INSN_SIZE 15
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#define X86_MODRM_MOD(modrm) (((modrm) & 0xc0) >> 6)
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#define X86_MODRM_REG(modrm) (((modrm) & 0x38) >> 3)
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#define X86_MODRM_RM(modrm) ((modrm) & 0x07)
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#define X86_SIB_SCALE(sib) (((sib) & 0xc0) >> 6)
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#define X86_SIB_INDEX(sib) (((sib) & 0x38) >> 3)
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#define X86_SIB_BASE(sib) ((sib) & 0x07)
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#define X86_REX_W(rex) ((rex) & 8)
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#define X86_REX_R(rex) ((rex) & 4)
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#define X86_REX_X(rex) ((rex) & 2)
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#define X86_REX_B(rex) ((rex) & 1)
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/* VEX bit flags */
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#define X86_VEX_W(vex) ((vex) & 0x80) /* VEX3 Byte2 */
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#define X86_VEX_R(vex) ((vex) & 0x80) /* VEX2/3 Byte1 */
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#define X86_VEX_X(vex) ((vex) & 0x40) /* VEX3 Byte1 */
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#define X86_VEX_B(vex) ((vex) & 0x20) /* VEX3 Byte1 */
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#define X86_VEX_L(vex) ((vex) & 0x04) /* VEX3 Byte2, VEX2 Byte1 */
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/* VEX bit fields */
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#define X86_EVEX_M(vex) ((vex) & 0x03) /* EVEX Byte1 */
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#define X86_VEX3_M(vex) ((vex) & 0x1f) /* VEX3 Byte1 */
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#define X86_VEX2_M 1 /* VEX2.M always 1 */
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#define X86_VEX_V(vex) (((vex) & 0x78) >> 3) /* VEX3 Byte2, VEX2 Byte1 */
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#define X86_VEX_P(vex) ((vex) & 0x03) /* VEX3 Byte2, VEX2 Byte1 */
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#define X86_VEX_M_MAX 0x1f /* VEX3.M Maximum value */
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extern void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64);
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extern int insn_get_prefixes(struct insn *insn);
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extern int insn_get_opcode(struct insn *insn);
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extern int insn_get_modrm(struct insn *insn);
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extern int insn_get_sib(struct insn *insn);
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extern int insn_get_displacement(struct insn *insn);
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extern int insn_get_immediate(struct insn *insn);
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extern int insn_get_length(struct insn *insn);
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enum insn_mode {
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INSN_MODE_32,
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INSN_MODE_64,
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/* Mode is determined by the current kernel build. */
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INSN_MODE_KERN,
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INSN_NUM_MODES,
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};
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extern int insn_decode(struct insn *insn, const void *kaddr, int buf_len, enum insn_mode m);
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#define insn_decode_kernel(_insn, _ptr) insn_decode((_insn), (_ptr), MAX_INSN_SIZE, INSN_MODE_KERN)
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/* Attribute will be determined after getting ModRM (for opcode groups) */
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static inline void insn_get_attribute(struct insn *insn)
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{
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insn_get_modrm(insn);
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}
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/* Instruction uses RIP-relative addressing */
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extern int insn_rip_relative(struct insn *insn);
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static inline int insn_is_avx(struct insn *insn)
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{
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if (!insn->prefixes.got)
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insn_get_prefixes(insn);
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return (insn->vex_prefix.value != 0);
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}
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static inline int insn_is_evex(struct insn *insn)
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{
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if (!insn->prefixes.got)
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insn_get_prefixes(insn);
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return (insn->vex_prefix.nbytes == 4);
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}
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static inline int insn_has_emulate_prefix(struct insn *insn)
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{
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return !!insn->emulate_prefix_size;
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}
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static inline insn_byte_t insn_vex_m_bits(struct insn *insn)
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{
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if (insn->vex_prefix.nbytes == 2) /* 2 bytes VEX */
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return X86_VEX2_M;
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else if (insn->vex_prefix.nbytes == 3) /* 3 bytes VEX */
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return X86_VEX3_M(insn->vex_prefix.bytes[1]);
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else /* EVEX */
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return X86_EVEX_M(insn->vex_prefix.bytes[1]);
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}
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static inline insn_byte_t insn_vex_p_bits(struct insn *insn)
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{
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if (insn->vex_prefix.nbytes == 2) /* 2 bytes VEX */
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return X86_VEX_P(insn->vex_prefix.bytes[1]);
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else
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return X86_VEX_P(insn->vex_prefix.bytes[2]);
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}
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/* Get the last prefix id from last prefix or VEX prefix */
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static inline int insn_last_prefix_id(struct insn *insn)
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{
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if (insn_is_avx(insn))
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return insn_vex_p_bits(insn); /* VEX_p is a SIMD prefix id */
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if (insn->prefixes.bytes[3])
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return inat_get_last_prefix_id(insn->prefixes.bytes[3]);
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return 0;
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}
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/* Offset of each field from kaddr */
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static inline int insn_offset_rex_prefix(struct insn *insn)
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{
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return insn->prefixes.nbytes;
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}
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static inline int insn_offset_vex_prefix(struct insn *insn)
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{
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return insn_offset_rex_prefix(insn) + insn->rex_prefix.nbytes;
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}
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static inline int insn_offset_opcode(struct insn *insn)
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{
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return insn_offset_vex_prefix(insn) + insn->vex_prefix.nbytes;
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}
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static inline int insn_offset_modrm(struct insn *insn)
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{
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return insn_offset_opcode(insn) + insn->opcode.nbytes;
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}
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static inline int insn_offset_sib(struct insn *insn)
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{
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return insn_offset_modrm(insn) + insn->modrm.nbytes;
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}
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static inline int insn_offset_displacement(struct insn *insn)
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{
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return insn_offset_sib(insn) + insn->sib.nbytes;
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}
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static inline int insn_offset_immediate(struct insn *insn)
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{
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return insn_offset_displacement(insn) + insn->displacement.nbytes;
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}
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/**
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* for_each_insn_prefix() -- Iterate prefixes in the instruction
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* @insn: Pointer to struct insn.
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* @idx: Index storage.
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* @prefix: Prefix byte.
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*
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* Iterate prefix bytes of given @insn. Each prefix byte is stored in @prefix
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* and the index is stored in @idx (note that this @idx is just for a cursor,
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* do not change it.)
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* Since prefixes.nbytes can be bigger than 4 if some prefixes
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* are repeated, it cannot be used for looping over the prefixes.
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*/
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#define for_each_insn_prefix(insn, idx, prefix) \
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for (idx = 0; idx < ARRAY_SIZE(insn->prefixes.bytes) && (prefix = insn->prefixes.bytes[idx]) != 0; idx++)
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#define POP_SS_OPCODE 0x1f
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#define MOV_SREG_OPCODE 0x8e
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/*
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* Intel SDM Vol.3A 6.8.3 states;
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* "Any single-step trap that would be delivered following the MOV to SS
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* instruction or POP to SS instruction (because EFLAGS.TF is 1) is
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* suppressed."
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* This function returns true if @insn is MOV SS or POP SS. On these
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* instructions, single stepping is suppressed.
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*/
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static inline int insn_masking_exception(struct insn *insn)
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{
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return insn->opcode.bytes[0] == POP_SS_OPCODE ||
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(insn->opcode.bytes[0] == MOV_SREG_OPCODE &&
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X86_MODRM_REG(insn->modrm.bytes[0]) == 2);
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}
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#endif /* _ASM_X86_INSN_H */
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