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0f923e0712
* Invert the mask of bits that we pick from L2 in
nested_vmcb02_prepare_control
* Invert and explicitly use VIRQ related bits bitmask in svm_clear_vintr
This fixes a security issue that allowed a malicious L1 to run L2 with
AVIC enabled, which allowed the L2 to exploit the uninitialized and enabled
AVIC to read/write the host physical memory at some offsets.
Fixes: 3d6368ef58 ("KVM: SVM: Add VMRUN handler")
Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
450 lines
10 KiB
C
450 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __SVM_H
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#define __SVM_H
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#include <uapi/asm/svm.h>
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#include <uapi/asm/kvm.h>
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/*
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* 32-bit intercept words in the VMCB Control Area, starting
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* at Byte offset 000h.
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*/
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enum intercept_words {
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INTERCEPT_CR = 0,
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INTERCEPT_DR,
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INTERCEPT_EXCEPTION,
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INTERCEPT_WORD3,
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INTERCEPT_WORD4,
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INTERCEPT_WORD5,
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MAX_INTERCEPT,
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};
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enum {
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/* Byte offset 000h (word 0) */
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INTERCEPT_CR0_READ = 0,
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INTERCEPT_CR3_READ = 3,
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INTERCEPT_CR4_READ = 4,
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INTERCEPT_CR8_READ = 8,
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INTERCEPT_CR0_WRITE = 16,
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INTERCEPT_CR3_WRITE = 16 + 3,
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INTERCEPT_CR4_WRITE = 16 + 4,
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INTERCEPT_CR8_WRITE = 16 + 8,
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/* Byte offset 004h (word 1) */
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INTERCEPT_DR0_READ = 32,
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INTERCEPT_DR1_READ,
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INTERCEPT_DR2_READ,
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INTERCEPT_DR3_READ,
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INTERCEPT_DR4_READ,
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INTERCEPT_DR5_READ,
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INTERCEPT_DR6_READ,
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INTERCEPT_DR7_READ,
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INTERCEPT_DR0_WRITE = 48,
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INTERCEPT_DR1_WRITE,
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INTERCEPT_DR2_WRITE,
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INTERCEPT_DR3_WRITE,
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INTERCEPT_DR4_WRITE,
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INTERCEPT_DR5_WRITE,
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INTERCEPT_DR6_WRITE,
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INTERCEPT_DR7_WRITE,
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/* Byte offset 008h (word 2) */
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INTERCEPT_EXCEPTION_OFFSET = 64,
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/* Byte offset 00Ch (word 3) */
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INTERCEPT_INTR = 96,
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INTERCEPT_NMI,
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INTERCEPT_SMI,
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INTERCEPT_INIT,
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INTERCEPT_VINTR,
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INTERCEPT_SELECTIVE_CR0,
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INTERCEPT_STORE_IDTR,
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INTERCEPT_STORE_GDTR,
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INTERCEPT_STORE_LDTR,
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INTERCEPT_STORE_TR,
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INTERCEPT_LOAD_IDTR,
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INTERCEPT_LOAD_GDTR,
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INTERCEPT_LOAD_LDTR,
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INTERCEPT_LOAD_TR,
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INTERCEPT_RDTSC,
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INTERCEPT_RDPMC,
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INTERCEPT_PUSHF,
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INTERCEPT_POPF,
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INTERCEPT_CPUID,
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INTERCEPT_RSM,
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INTERCEPT_IRET,
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INTERCEPT_INTn,
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INTERCEPT_INVD,
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INTERCEPT_PAUSE,
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INTERCEPT_HLT,
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INTERCEPT_INVLPG,
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INTERCEPT_INVLPGA,
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INTERCEPT_IOIO_PROT,
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INTERCEPT_MSR_PROT,
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INTERCEPT_TASK_SWITCH,
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INTERCEPT_FERR_FREEZE,
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INTERCEPT_SHUTDOWN,
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/* Byte offset 010h (word 4) */
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INTERCEPT_VMRUN = 128,
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INTERCEPT_VMMCALL,
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INTERCEPT_VMLOAD,
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INTERCEPT_VMSAVE,
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INTERCEPT_STGI,
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INTERCEPT_CLGI,
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INTERCEPT_SKINIT,
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INTERCEPT_RDTSCP,
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INTERCEPT_ICEBP,
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INTERCEPT_WBINVD,
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INTERCEPT_MONITOR,
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INTERCEPT_MWAIT,
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INTERCEPT_MWAIT_COND,
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INTERCEPT_XSETBV,
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INTERCEPT_RDPRU,
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TRAP_EFER_WRITE,
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TRAP_CR0_WRITE,
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TRAP_CR1_WRITE,
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TRAP_CR2_WRITE,
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TRAP_CR3_WRITE,
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TRAP_CR4_WRITE,
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TRAP_CR5_WRITE,
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TRAP_CR6_WRITE,
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TRAP_CR7_WRITE,
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TRAP_CR8_WRITE,
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/* Byte offset 014h (word 5) */
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INTERCEPT_INVLPGB = 160,
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INTERCEPT_INVLPGB_ILLEGAL,
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INTERCEPT_INVPCID,
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INTERCEPT_MCOMMIT,
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INTERCEPT_TLBSYNC,
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};
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struct __attribute__ ((__packed__)) vmcb_control_area {
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u32 intercepts[MAX_INTERCEPT];
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u32 reserved_1[15 - MAX_INTERCEPT];
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u16 pause_filter_thresh;
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u16 pause_filter_count;
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u64 iopm_base_pa;
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u64 msrpm_base_pa;
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u64 tsc_offset;
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u32 asid;
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u8 tlb_ctl;
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u8 reserved_2[3];
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u32 int_ctl;
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u32 int_vector;
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u32 int_state;
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u8 reserved_3[4];
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u32 exit_code;
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u32 exit_code_hi;
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u64 exit_info_1;
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u64 exit_info_2;
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u32 exit_int_info;
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u32 exit_int_info_err;
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u64 nested_ctl;
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u64 avic_vapic_bar;
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u64 ghcb_gpa;
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u32 event_inj;
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u32 event_inj_err;
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u64 nested_cr3;
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u64 virt_ext;
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u32 clean;
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u32 reserved_5;
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u64 next_rip;
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u8 insn_len;
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u8 insn_bytes[15];
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u64 avic_backing_page; /* Offset 0xe0 */
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u8 reserved_6[8]; /* Offset 0xe8 */
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u64 avic_logical_id; /* Offset 0xf0 */
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u64 avic_physical_id; /* Offset 0xf8 */
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u8 reserved_7[8];
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u64 vmsa_pa; /* Used for an SEV-ES guest */
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u8 reserved_8[720];
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/*
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* Offset 0x3e0, 32 bytes reserved
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* for use by hypervisor/software.
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*/
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u8 reserved_sw[32];
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};
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#define TLB_CONTROL_DO_NOTHING 0
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#define TLB_CONTROL_FLUSH_ALL_ASID 1
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#define TLB_CONTROL_FLUSH_ASID 3
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#define TLB_CONTROL_FLUSH_ASID_LOCAL 7
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#define V_TPR_MASK 0x0f
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#define V_IRQ_SHIFT 8
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#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
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#define V_GIF_SHIFT 9
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#define V_GIF_MASK (1 << V_GIF_SHIFT)
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#define V_INTR_PRIO_SHIFT 16
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#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
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#define V_IGN_TPR_SHIFT 20
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#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
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#define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK)
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#define V_INTR_MASKING_SHIFT 24
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#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
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#define V_GIF_ENABLE_SHIFT 25
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#define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
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#define AVIC_ENABLE_SHIFT 31
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#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
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#define LBR_CTL_ENABLE_MASK BIT_ULL(0)
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#define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
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#define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0)
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#define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1)
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#define SVM_IOIO_STR_SHIFT 2
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#define SVM_IOIO_REP_SHIFT 3
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#define SVM_IOIO_SIZE_SHIFT 4
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#define SVM_IOIO_ASIZE_SHIFT 7
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#define SVM_IOIO_TYPE_MASK 1
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#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
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#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
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#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
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#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
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#define SVM_VM_CR_VALID_MASK 0x001fULL
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#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
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#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
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#define SVM_NESTED_CTL_NP_ENABLE BIT(0)
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#define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
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#define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2)
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struct vmcb_seg {
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u16 selector;
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u16 attrib;
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u32 limit;
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u64 base;
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} __packed;
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struct vmcb_save_area {
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struct vmcb_seg es;
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struct vmcb_seg cs;
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struct vmcb_seg ss;
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struct vmcb_seg ds;
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struct vmcb_seg fs;
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struct vmcb_seg gs;
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struct vmcb_seg gdtr;
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struct vmcb_seg ldtr;
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struct vmcb_seg idtr;
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struct vmcb_seg tr;
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u8 reserved_1[43];
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u8 cpl;
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u8 reserved_2[4];
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u64 efer;
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u8 reserved_3[104];
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u64 xss; /* Valid for SEV-ES only */
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u64 cr4;
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u64 cr3;
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u64 cr0;
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u64 dr7;
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u64 dr6;
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u64 rflags;
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u64 rip;
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u8 reserved_4[88];
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u64 rsp;
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u8 reserved_5[24];
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u64 rax;
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u64 star;
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u64 lstar;
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u64 cstar;
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u64 sfmask;
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u64 kernel_gs_base;
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u64 sysenter_cs;
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u64 sysenter_esp;
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u64 sysenter_eip;
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u64 cr2;
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u8 reserved_6[32];
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u64 g_pat;
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u64 dbgctl;
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u64 br_from;
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u64 br_to;
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u64 last_excp_from;
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u64 last_excp_to;
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/*
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* The following part of the save area is valid only for
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* SEV-ES guests when referenced through the GHCB or for
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* saving to the host save area.
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*/
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u8 reserved_7[72];
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u32 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */
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u8 reserved_7b[4];
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u32 pkru;
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u8 reserved_7a[20];
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u64 reserved_8; /* rax already available at 0x01f8 */
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u64 rcx;
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u64 rdx;
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u64 rbx;
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u64 reserved_9; /* rsp already available at 0x01d8 */
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u64 rbp;
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u64 rsi;
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u64 rdi;
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u64 r8;
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u64 r9;
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u64 r10;
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u64 r11;
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u64 r12;
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u64 r13;
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u64 r14;
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u64 r15;
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u8 reserved_10[16];
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u64 sw_exit_code;
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u64 sw_exit_info_1;
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u64 sw_exit_info_2;
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u64 sw_scratch;
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u8 reserved_11[56];
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u64 xcr0;
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u8 valid_bitmap[16];
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u64 x87_state_gpa;
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} __packed;
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struct ghcb {
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struct vmcb_save_area save;
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u8 reserved_save[2048 - sizeof(struct vmcb_save_area)];
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u8 shared_buffer[2032];
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u8 reserved_1[10];
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u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */
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u32 ghcb_usage;
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} __packed;
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#define EXPECTED_VMCB_SAVE_AREA_SIZE 1032
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#define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024
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#define EXPECTED_GHCB_SIZE PAGE_SIZE
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static inline void __unused_size_checks(void)
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{
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BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE);
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BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
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BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE);
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}
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struct vmcb {
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struct vmcb_control_area control;
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struct vmcb_save_area save;
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} __packed;
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#define SVM_CPUID_FUNC 0x8000000a
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#define SVM_VM_CR_SVM_DISABLE 4
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#define SVM_SELECTOR_S_SHIFT 4
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#define SVM_SELECTOR_DPL_SHIFT 5
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#define SVM_SELECTOR_P_SHIFT 7
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#define SVM_SELECTOR_AVL_SHIFT 8
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#define SVM_SELECTOR_L_SHIFT 9
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#define SVM_SELECTOR_DB_SHIFT 10
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#define SVM_SELECTOR_G_SHIFT 11
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#define SVM_SELECTOR_TYPE_MASK (0xf)
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#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
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#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
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#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
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#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
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#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
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#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
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#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
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#define SVM_SELECTOR_WRITE_MASK (1 << 1)
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#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
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#define SVM_SELECTOR_CODE_MASK (1 << 3)
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#define SVM_EVTINJ_VEC_MASK 0xff
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#define SVM_EVTINJ_TYPE_SHIFT 8
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#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
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#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
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#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
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#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
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#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
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#define SVM_EVTINJ_VALID (1 << 31)
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#define SVM_EVTINJ_VALID_ERR (1 << 11)
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#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
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#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
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#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
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#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
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#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
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#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
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#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
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#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
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#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
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#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
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#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
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#define SVM_EXITINFO_REG_MASK 0x0F
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#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
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/* GHCB Accessor functions */
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#define GHCB_BITMAP_IDX(field) \
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(offsetof(struct vmcb_save_area, field) / sizeof(u64))
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#define DEFINE_GHCB_ACCESSORS(field) \
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static inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
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{ \
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return test_bit(GHCB_BITMAP_IDX(field), \
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(unsigned long *)&ghcb->save.valid_bitmap); \
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} \
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\
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static inline u64 ghcb_get_##field(struct ghcb *ghcb) \
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{ \
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return ghcb->save.field; \
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} \
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\
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static inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \
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{ \
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return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0; \
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} \
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\
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static inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \
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{ \
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__set_bit(GHCB_BITMAP_IDX(field), \
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(unsigned long *)&ghcb->save.valid_bitmap); \
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ghcb->save.field = value; \
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}
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DEFINE_GHCB_ACCESSORS(cpl)
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DEFINE_GHCB_ACCESSORS(rip)
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DEFINE_GHCB_ACCESSORS(rsp)
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DEFINE_GHCB_ACCESSORS(rax)
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DEFINE_GHCB_ACCESSORS(rcx)
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DEFINE_GHCB_ACCESSORS(rdx)
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DEFINE_GHCB_ACCESSORS(rbx)
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DEFINE_GHCB_ACCESSORS(rbp)
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DEFINE_GHCB_ACCESSORS(rsi)
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DEFINE_GHCB_ACCESSORS(rdi)
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DEFINE_GHCB_ACCESSORS(r8)
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DEFINE_GHCB_ACCESSORS(r9)
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DEFINE_GHCB_ACCESSORS(r10)
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DEFINE_GHCB_ACCESSORS(r11)
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DEFINE_GHCB_ACCESSORS(r12)
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DEFINE_GHCB_ACCESSORS(r13)
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DEFINE_GHCB_ACCESSORS(r14)
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DEFINE_GHCB_ACCESSORS(r15)
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DEFINE_GHCB_ACCESSORS(sw_exit_code)
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DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
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DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
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DEFINE_GHCB_ACCESSORS(sw_scratch)
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DEFINE_GHCB_ACCESSORS(xcr0)
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#endif
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