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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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![Linus Torvalds](/assets/img/avatar_default.png)
was a pretty active cycle for KVM. Changes include: - a lot of s390 changes: optimizations, support for migration, GDB support and more - ARM changes are pretty small: support for the PSCI 0.2 hypercall interface on both the guest and the host (the latter acked by Catalin) - initial POWER8 and little-endian host support - support for running u-boot on embedded POWER targets - pretty large changes to MIPS too, completing the userspace interface and improving the handling of virtualized timer hardware - for x86, a larger set of changes is scheduled for 3.17. Still, we have a few emulator bugfixes and support for running nested fully-virtualized Xen guests (para-virtualized Xen guests have always worked). And some optimizations too. The only missing architecture here is ia64. It's not a coincidence that support for KVM on ia64 is scheduled for removal in 3.17. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJTjtlBAAoJEBvWZb6bTYbyMOUP/2NAePghE3IjG99ikHFdn+BX BfrURsuR6GD0AhYQnBidBmpFbAmN/LwSJxv/M7sV7OBRWLu3qbt69DrPTU2e/FK1 j9q25peu8jRyHzJ1q9rBroo74nD9lQYuVr3uXNxxcg0DRnw14JHGlM3y8LDEknO8 W+gpWTeAQ+2AuOX98MpRbCRMuzziCSv5bP5FhBVnsWHiZfvMbcUrbeJt+zYSiDAZ 0tHm/5dFKzfj/vVrrnjD4EZcRr688Bs5rztG96hY6aoVJryjZGLtLp92wCWkRRmH CCvZwd245NmNthuKHzcs27/duSWfU0uOlu7AMrD44QYhzeDGyB/2nbCxbGqLLoBA nnOviXH4cC65/CnisZ79zfo979HbZcX+Lzg747EjBgCSxJmLlwgiG8yXtDvk5otB TH6GUeGDiEEPj//JD3XtgSz0sF2NvjREWRyemjDMvhz6JC/bLytXKb3sn+NXSj8m ujzF9eQoa4qKDcBL4IQYGTJ4z5nY3Pd68dHFIPHB7n82OxFLSQUBKxXw8/1fb5og VVb8PL4GOcmakQlAKtTMlFPmuy4bbL2r/2iV5xJiOZKmXIu8Hs1JezBE3SFAltbl 3cAGwSM9/dDkKxUbTFblyOE9bkKbg4WYmq0LkdzsPEomb3IZWntOT25rYnX+LrBz bAknaZpPiOrW11Et1htY =j5Od -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm into next Pull KVM updates from Paolo Bonzini: "At over 200 commits, covering almost all supported architectures, this was a pretty active cycle for KVM. Changes include: - a lot of s390 changes: optimizations, support for migration, GDB support and more - ARM changes are pretty small: support for the PSCI 0.2 hypercall interface on both the guest and the host (the latter acked by Catalin) - initial POWER8 and little-endian host support - support for running u-boot on embedded POWER targets - pretty large changes to MIPS too, completing the userspace interface and improving the handling of virtualized timer hardware - for x86, a larger set of changes is scheduled for 3.17. Still, we have a few emulator bugfixes and support for running nested fully-virtualized Xen guests (para-virtualized Xen guests have always worked). And some optimizations too. The only missing architecture here is ia64. It's not a coincidence that support for KVM on ia64 is scheduled for removal in 3.17" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (203 commits) KVM: add missing cleanup_srcu_struct KVM: PPC: Book3S PR: Rework SLB switching code KVM: PPC: Book3S PR: Use SLB entry 0 KVM: PPC: Book3S HV: Fix machine check delivery to guest KVM: PPC: Book3S HV: Work around POWER8 performance monitor bugs KVM: PPC: Book3S HV: Make sure we don't miss dirty pages KVM: PPC: Book3S HV: Fix dirty map for hugepages KVM: PPC: Book3S HV: Put huge-page HPTEs in rmap chain for base address KVM: PPC: Book3S HV: Fix check for running inside guest in global_invalidates() KVM: PPC: Book3S: Move KVM_REG_PPC_WORT to an unused register number KVM: PPC: Book3S: Add ONE_REG register names that were missed KVM: PPC: Add CAP to indicate hcall fixes KVM: PPC: MPIC: Reset IRQ source private members KVM: PPC: Graciously fail broken LE hypercalls PPC: ePAPR: Fix hypercall on LE guest KVM: PPC: BOOK3S: Remove open coded make_dsisr in alignment handler KVM: PPC: BOOK3S: Always use the saved DAR value PPC: KVM: Make NX bit available with magic page KVM: PPC: Disable NX for old magic page using guests KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest ...
925 lines
25 KiB
C
925 lines
25 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* Copyright 2010-2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
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*/
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/hugetlb.h>
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#include <linux/module.h>
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#include <asm/tlbflush.h>
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#include <asm/kvm_ppc.h>
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#include <asm/kvm_book3s.h>
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#include <asm/mmu-hash64.h>
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#include <asm/hvcall.h>
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#include <asm/synch.h>
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#include <asm/ppc-opcode.h>
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/* Translate address of a vmalloc'd thing to a linear map address */
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static void *real_vmalloc_addr(void *x)
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{
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unsigned long addr = (unsigned long) x;
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pte_t *p;
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p = find_linux_pte_or_hugepte(swapper_pg_dir, addr, NULL);
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if (!p || !pte_present(*p))
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return NULL;
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/* assume we don't have huge pages in vmalloc space... */
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addr = (pte_pfn(*p) << PAGE_SHIFT) | (addr & ~PAGE_MASK);
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return __va(addr);
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}
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/* Return 1 if we need to do a global tlbie, 0 if we can use tlbiel */
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static int global_invalidates(struct kvm *kvm, unsigned long flags)
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{
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int global;
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/*
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* If there is only one vcore, and it's currently running,
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* as indicated by local_paca->kvm_hstate.kvm_vcpu being set,
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* we can use tlbiel as long as we mark all other physical
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* cores as potentially having stale TLB entries for this lpid.
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* If we're not using MMU notifiers, we never take pages away
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* from the guest, so we can use tlbiel if requested.
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* Otherwise, don't use tlbiel.
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*/
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if (kvm->arch.online_vcores == 1 && local_paca->kvm_hstate.kvm_vcpu)
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global = 0;
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else if (kvm->arch.using_mmu_notifiers)
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global = 1;
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else
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global = !(flags & H_LOCAL);
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if (!global) {
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/* any other core might now have stale TLB entries... */
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smp_wmb();
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cpumask_setall(&kvm->arch.need_tlb_flush);
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cpumask_clear_cpu(local_paca->kvm_hstate.kvm_vcore->pcpu,
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&kvm->arch.need_tlb_flush);
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}
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return global;
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}
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/*
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* Add this HPTE into the chain for the real page.
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* Must be called with the chain locked; it unlocks the chain.
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*/
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void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev,
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unsigned long *rmap, long pte_index, int realmode)
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{
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struct revmap_entry *head, *tail;
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unsigned long i;
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if (*rmap & KVMPPC_RMAP_PRESENT) {
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i = *rmap & KVMPPC_RMAP_INDEX;
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head = &kvm->arch.revmap[i];
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if (realmode)
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head = real_vmalloc_addr(head);
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tail = &kvm->arch.revmap[head->back];
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if (realmode)
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tail = real_vmalloc_addr(tail);
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rev->forw = i;
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rev->back = head->back;
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tail->forw = pte_index;
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head->back = pte_index;
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} else {
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rev->forw = rev->back = pte_index;
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*rmap = (*rmap & ~KVMPPC_RMAP_INDEX) |
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pte_index | KVMPPC_RMAP_PRESENT;
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}
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unlock_rmap(rmap);
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}
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EXPORT_SYMBOL_GPL(kvmppc_add_revmap_chain);
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/* Remove this HPTE from the chain for a real page */
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static void remove_revmap_chain(struct kvm *kvm, long pte_index,
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struct revmap_entry *rev,
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unsigned long hpte_v, unsigned long hpte_r)
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{
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struct revmap_entry *next, *prev;
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unsigned long gfn, ptel, head;
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struct kvm_memory_slot *memslot;
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unsigned long *rmap;
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unsigned long rcbits;
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rcbits = hpte_r & (HPTE_R_R | HPTE_R_C);
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ptel = rev->guest_rpte |= rcbits;
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gfn = hpte_rpn(ptel, hpte_page_size(hpte_v, ptel));
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memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
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if (!memslot)
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return;
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rmap = real_vmalloc_addr(&memslot->arch.rmap[gfn - memslot->base_gfn]);
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lock_rmap(rmap);
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head = *rmap & KVMPPC_RMAP_INDEX;
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next = real_vmalloc_addr(&kvm->arch.revmap[rev->forw]);
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prev = real_vmalloc_addr(&kvm->arch.revmap[rev->back]);
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next->back = rev->back;
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prev->forw = rev->forw;
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if (head == pte_index) {
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head = rev->forw;
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if (head == pte_index)
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*rmap &= ~(KVMPPC_RMAP_PRESENT | KVMPPC_RMAP_INDEX);
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else
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*rmap = (*rmap & ~KVMPPC_RMAP_INDEX) | head;
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}
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*rmap |= rcbits << KVMPPC_RMAP_RC_SHIFT;
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unlock_rmap(rmap);
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}
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static pte_t lookup_linux_pte_and_update(pgd_t *pgdir, unsigned long hva,
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int writing, unsigned long *pte_sizep)
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{
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pte_t *ptep;
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unsigned long ps = *pte_sizep;
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unsigned int hugepage_shift;
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ptep = find_linux_pte_or_hugepte(pgdir, hva, &hugepage_shift);
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if (!ptep)
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return __pte(0);
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if (hugepage_shift)
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*pte_sizep = 1ul << hugepage_shift;
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else
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*pte_sizep = PAGE_SIZE;
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if (ps > *pte_sizep)
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return __pte(0);
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return kvmppc_read_update_linux_pte(ptep, writing, hugepage_shift);
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}
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static inline void unlock_hpte(unsigned long *hpte, unsigned long hpte_v)
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{
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asm volatile(PPC_RELEASE_BARRIER "" : : : "memory");
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hpte[0] = hpte_v;
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}
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long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags,
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long pte_index, unsigned long pteh, unsigned long ptel,
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pgd_t *pgdir, bool realmode, unsigned long *pte_idx_ret)
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{
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unsigned long i, pa, gpa, gfn, psize;
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unsigned long slot_fn, hva;
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unsigned long *hpte;
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struct revmap_entry *rev;
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unsigned long g_ptel;
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struct kvm_memory_slot *memslot;
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unsigned long *physp, pte_size;
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unsigned long is_io;
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unsigned long *rmap;
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pte_t pte;
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unsigned int writing;
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unsigned long mmu_seq;
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unsigned long rcbits;
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psize = hpte_page_size(pteh, ptel);
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if (!psize)
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return H_PARAMETER;
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writing = hpte_is_writable(ptel);
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pteh &= ~(HPTE_V_HVLOCK | HPTE_V_ABSENT | HPTE_V_VALID);
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ptel &= ~HPTE_GR_RESERVED;
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g_ptel = ptel;
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/* used later to detect if we might have been invalidated */
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mmu_seq = kvm->mmu_notifier_seq;
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smp_rmb();
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/* Find the memslot (if any) for this address */
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gpa = (ptel & HPTE_R_RPN) & ~(psize - 1);
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gfn = gpa >> PAGE_SHIFT;
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memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
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pa = 0;
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is_io = ~0ul;
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rmap = NULL;
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if (!(memslot && !(memslot->flags & KVM_MEMSLOT_INVALID))) {
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/* PPC970 can't do emulated MMIO */
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if (!cpu_has_feature(CPU_FTR_ARCH_206))
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return H_PARAMETER;
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/* Emulated MMIO - mark this with key=31 */
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pteh |= HPTE_V_ABSENT;
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ptel |= HPTE_R_KEY_HI | HPTE_R_KEY_LO;
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goto do_insert;
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}
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/* Check if the requested page fits entirely in the memslot. */
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if (!slot_is_aligned(memslot, psize))
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return H_PARAMETER;
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slot_fn = gfn - memslot->base_gfn;
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rmap = &memslot->arch.rmap[slot_fn];
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if (!kvm->arch.using_mmu_notifiers) {
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physp = memslot->arch.slot_phys;
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if (!physp)
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return H_PARAMETER;
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physp += slot_fn;
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if (realmode)
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physp = real_vmalloc_addr(physp);
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pa = *physp;
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if (!pa)
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return H_TOO_HARD;
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is_io = pa & (HPTE_R_I | HPTE_R_W);
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pte_size = PAGE_SIZE << (pa & KVMPPC_PAGE_ORDER_MASK);
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pa &= PAGE_MASK;
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pa |= gpa & ~PAGE_MASK;
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} else {
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/* Translate to host virtual address */
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hva = __gfn_to_hva_memslot(memslot, gfn);
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/* Look up the Linux PTE for the backing page */
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pte_size = psize;
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pte = lookup_linux_pte_and_update(pgdir, hva, writing,
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&pte_size);
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if (pte_present(pte) && !pte_numa(pte)) {
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if (writing && !pte_write(pte))
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/* make the actual HPTE be read-only */
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ptel = hpte_make_readonly(ptel);
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is_io = hpte_cache_bits(pte_val(pte));
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pa = pte_pfn(pte) << PAGE_SHIFT;
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pa |= hva & (pte_size - 1);
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pa |= gpa & ~PAGE_MASK;
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}
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}
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if (pte_size < psize)
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return H_PARAMETER;
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ptel &= ~(HPTE_R_PP0 - psize);
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ptel |= pa;
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if (pa)
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pteh |= HPTE_V_VALID;
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else
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pteh |= HPTE_V_ABSENT;
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/* Check WIMG */
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if (is_io != ~0ul && !hpte_cache_flags_ok(ptel, is_io)) {
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if (is_io)
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return H_PARAMETER;
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/*
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* Allow guest to map emulated device memory as
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* uncacheable, but actually make it cacheable.
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*/
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ptel &= ~(HPTE_R_W|HPTE_R_I|HPTE_R_G);
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ptel |= HPTE_R_M;
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}
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/* Find and lock the HPTEG slot to use */
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do_insert:
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if (pte_index >= kvm->arch.hpt_npte)
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return H_PARAMETER;
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if (likely((flags & H_EXACT) == 0)) {
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pte_index &= ~7UL;
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hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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for (i = 0; i < 8; ++i) {
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if ((*hpte & HPTE_V_VALID) == 0 &&
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try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
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HPTE_V_ABSENT))
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break;
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hpte += 2;
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}
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if (i == 8) {
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/*
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* Since try_lock_hpte doesn't retry (not even stdcx.
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* failures), it could be that there is a free slot
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* but we transiently failed to lock it. Try again,
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* actually locking each slot and checking it.
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*/
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hpte -= 16;
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for (i = 0; i < 8; ++i) {
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while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
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cpu_relax();
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if (!(*hpte & (HPTE_V_VALID | HPTE_V_ABSENT)))
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break;
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*hpte &= ~HPTE_V_HVLOCK;
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hpte += 2;
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}
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if (i == 8)
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return H_PTEG_FULL;
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}
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pte_index += i;
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} else {
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hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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if (!try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
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HPTE_V_ABSENT)) {
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/* Lock the slot and check again */
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while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
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cpu_relax();
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if (*hpte & (HPTE_V_VALID | HPTE_V_ABSENT)) {
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*hpte &= ~HPTE_V_HVLOCK;
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return H_PTEG_FULL;
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}
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}
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}
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/* Save away the guest's idea of the second HPTE dword */
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rev = &kvm->arch.revmap[pte_index];
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if (realmode)
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rev = real_vmalloc_addr(rev);
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if (rev) {
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rev->guest_rpte = g_ptel;
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note_hpte_modification(kvm, rev);
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}
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/* Link HPTE into reverse-map chain */
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if (pteh & HPTE_V_VALID) {
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if (realmode)
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rmap = real_vmalloc_addr(rmap);
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lock_rmap(rmap);
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/* Check for pending invalidations under the rmap chain lock */
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if (kvm->arch.using_mmu_notifiers &&
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mmu_notifier_retry(kvm, mmu_seq)) {
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/* inval in progress, write a non-present HPTE */
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pteh |= HPTE_V_ABSENT;
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pteh &= ~HPTE_V_VALID;
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unlock_rmap(rmap);
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} else {
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kvmppc_add_revmap_chain(kvm, rev, rmap, pte_index,
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realmode);
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/* Only set R/C in real HPTE if already set in *rmap */
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rcbits = *rmap >> KVMPPC_RMAP_RC_SHIFT;
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ptel &= rcbits | ~(HPTE_R_R | HPTE_R_C);
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}
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}
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hpte[1] = ptel;
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/* Write the first HPTE dword, unlocking the HPTE and making it valid */
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eieio();
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hpte[0] = pteh;
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asm volatile("ptesync" : : : "memory");
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*pte_idx_ret = pte_index;
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return H_SUCCESS;
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}
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EXPORT_SYMBOL_GPL(kvmppc_do_h_enter);
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long kvmppc_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
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long pte_index, unsigned long pteh, unsigned long ptel)
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{
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return kvmppc_do_h_enter(vcpu->kvm, flags, pte_index, pteh, ptel,
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vcpu->arch.pgdir, true, &vcpu->arch.gpr[4]);
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}
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#ifdef __BIG_ENDIAN__
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#define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token))
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#else
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#define LOCK_TOKEN (*(u32 *)(&get_paca()->paca_index))
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#endif
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static inline int try_lock_tlbie(unsigned int *lock)
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{
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unsigned int tmp, old;
|
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unsigned int token = LOCK_TOKEN;
|
|
|
|
asm volatile("1:lwarx %1,0,%2\n"
|
|
" cmpwi cr0,%1,0\n"
|
|
" bne 2f\n"
|
|
" stwcx. %3,0,%2\n"
|
|
" bne- 1b\n"
|
|
" isync\n"
|
|
"2:"
|
|
: "=&r" (tmp), "=&r" (old)
|
|
: "r" (lock), "r" (token)
|
|
: "cc", "memory");
|
|
return old == 0;
|
|
}
|
|
|
|
/*
|
|
* tlbie/tlbiel is a bit different on the PPC970 compared to later
|
|
* processors such as POWER7; the large page bit is in the instruction
|
|
* not RB, and the top 16 bits and the bottom 12 bits of the VA
|
|
* in RB must be 0.
|
|
*/
|
|
static void do_tlbies_970(struct kvm *kvm, unsigned long *rbvalues,
|
|
long npages, int global, bool need_sync)
|
|
{
|
|
long i;
|
|
|
|
if (global) {
|
|
while (!try_lock_tlbie(&kvm->arch.tlbie_lock))
|
|
cpu_relax();
|
|
if (need_sync)
|
|
asm volatile("ptesync" : : : "memory");
|
|
for (i = 0; i < npages; ++i) {
|
|
unsigned long rb = rbvalues[i];
|
|
|
|
if (rb & 1) /* large page */
|
|
asm volatile("tlbie %0,1" : :
|
|
"r" (rb & 0x0000fffffffff000ul));
|
|
else
|
|
asm volatile("tlbie %0,0" : :
|
|
"r" (rb & 0x0000fffffffff000ul));
|
|
}
|
|
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
|
|
kvm->arch.tlbie_lock = 0;
|
|
} else {
|
|
if (need_sync)
|
|
asm volatile("ptesync" : : : "memory");
|
|
for (i = 0; i < npages; ++i) {
|
|
unsigned long rb = rbvalues[i];
|
|
|
|
if (rb & 1) /* large page */
|
|
asm volatile("tlbiel %0,1" : :
|
|
"r" (rb & 0x0000fffffffff000ul));
|
|
else
|
|
asm volatile("tlbiel %0,0" : :
|
|
"r" (rb & 0x0000fffffffff000ul));
|
|
}
|
|
asm volatile("ptesync" : : : "memory");
|
|
}
|
|
}
|
|
|
|
static void do_tlbies(struct kvm *kvm, unsigned long *rbvalues,
|
|
long npages, int global, bool need_sync)
|
|
{
|
|
long i;
|
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_201)) {
|
|
/* PPC970 tlbie instruction is a bit different */
|
|
do_tlbies_970(kvm, rbvalues, npages, global, need_sync);
|
|
return;
|
|
}
|
|
if (global) {
|
|
while (!try_lock_tlbie(&kvm->arch.tlbie_lock))
|
|
cpu_relax();
|
|
if (need_sync)
|
|
asm volatile("ptesync" : : : "memory");
|
|
for (i = 0; i < npages; ++i)
|
|
asm volatile(PPC_TLBIE(%1,%0) : :
|
|
"r" (rbvalues[i]), "r" (kvm->arch.lpid));
|
|
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
|
|
kvm->arch.tlbie_lock = 0;
|
|
} else {
|
|
if (need_sync)
|
|
asm volatile("ptesync" : : : "memory");
|
|
for (i = 0; i < npages; ++i)
|
|
asm volatile("tlbiel %0" : : "r" (rbvalues[i]));
|
|
asm volatile("ptesync" : : : "memory");
|
|
}
|
|
}
|
|
|
|
long kvmppc_do_h_remove(struct kvm *kvm, unsigned long flags,
|
|
unsigned long pte_index, unsigned long avpn,
|
|
unsigned long *hpret)
|
|
{
|
|
unsigned long *hpte;
|
|
unsigned long v, r, rb;
|
|
struct revmap_entry *rev;
|
|
|
|
if (pte_index >= kvm->arch.hpt_npte)
|
|
return H_PARAMETER;
|
|
hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
|
|
while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
|
|
cpu_relax();
|
|
if ((hpte[0] & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
|
|
((flags & H_AVPN) && (hpte[0] & ~0x7fUL) != avpn) ||
|
|
((flags & H_ANDCOND) && (hpte[0] & avpn) != 0)) {
|
|
hpte[0] &= ~HPTE_V_HVLOCK;
|
|
return H_NOT_FOUND;
|
|
}
|
|
|
|
rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
|
|
v = hpte[0] & ~HPTE_V_HVLOCK;
|
|
if (v & HPTE_V_VALID) {
|
|
hpte[0] &= ~HPTE_V_VALID;
|
|
rb = compute_tlbie_rb(v, hpte[1], pte_index);
|
|
do_tlbies(kvm, &rb, 1, global_invalidates(kvm, flags), true);
|
|
/* Read PTE low word after tlbie to get final R/C values */
|
|
remove_revmap_chain(kvm, pte_index, rev, v, hpte[1]);
|
|
}
|
|
r = rev->guest_rpte & ~HPTE_GR_RESERVED;
|
|
note_hpte_modification(kvm, rev);
|
|
unlock_hpte(hpte, 0);
|
|
|
|
hpret[0] = v;
|
|
hpret[1] = r;
|
|
return H_SUCCESS;
|
|
}
|
|
EXPORT_SYMBOL_GPL(kvmppc_do_h_remove);
|
|
|
|
long kvmppc_h_remove(struct kvm_vcpu *vcpu, unsigned long flags,
|
|
unsigned long pte_index, unsigned long avpn)
|
|
{
|
|
return kvmppc_do_h_remove(vcpu->kvm, flags, pte_index, avpn,
|
|
&vcpu->arch.gpr[4]);
|
|
}
|
|
|
|
long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm *kvm = vcpu->kvm;
|
|
unsigned long *args = &vcpu->arch.gpr[4];
|
|
unsigned long *hp, *hptes[4], tlbrb[4];
|
|
long int i, j, k, n, found, indexes[4];
|
|
unsigned long flags, req, pte_index, rcbits;
|
|
int global;
|
|
long int ret = H_SUCCESS;
|
|
struct revmap_entry *rev, *revs[4];
|
|
|
|
global = global_invalidates(kvm, 0);
|
|
for (i = 0; i < 4 && ret == H_SUCCESS; ) {
|
|
n = 0;
|
|
for (; i < 4; ++i) {
|
|
j = i * 2;
|
|
pte_index = args[j];
|
|
flags = pte_index >> 56;
|
|
pte_index &= ((1ul << 56) - 1);
|
|
req = flags >> 6;
|
|
flags &= 3;
|
|
if (req == 3) { /* no more requests */
|
|
i = 4;
|
|
break;
|
|
}
|
|
if (req != 1 || flags == 3 ||
|
|
pte_index >= kvm->arch.hpt_npte) {
|
|
/* parameter error */
|
|
args[j] = ((0xa0 | flags) << 56) + pte_index;
|
|
ret = H_PARAMETER;
|
|
break;
|
|
}
|
|
hp = (unsigned long *)
|
|
(kvm->arch.hpt_virt + (pte_index << 4));
|
|
/* to avoid deadlock, don't spin except for first */
|
|
if (!try_lock_hpte(hp, HPTE_V_HVLOCK)) {
|
|
if (n)
|
|
break;
|
|
while (!try_lock_hpte(hp, HPTE_V_HVLOCK))
|
|
cpu_relax();
|
|
}
|
|
found = 0;
|
|
if (hp[0] & (HPTE_V_ABSENT | HPTE_V_VALID)) {
|
|
switch (flags & 3) {
|
|
case 0: /* absolute */
|
|
found = 1;
|
|
break;
|
|
case 1: /* andcond */
|
|
if (!(hp[0] & args[j + 1]))
|
|
found = 1;
|
|
break;
|
|
case 2: /* AVPN */
|
|
if ((hp[0] & ~0x7fUL) == args[j + 1])
|
|
found = 1;
|
|
break;
|
|
}
|
|
}
|
|
if (!found) {
|
|
hp[0] &= ~HPTE_V_HVLOCK;
|
|
args[j] = ((0x90 | flags) << 56) + pte_index;
|
|
continue;
|
|
}
|
|
|
|
args[j] = ((0x80 | flags) << 56) + pte_index;
|
|
rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
|
|
note_hpte_modification(kvm, rev);
|
|
|
|
if (!(hp[0] & HPTE_V_VALID)) {
|
|
/* insert R and C bits from PTE */
|
|
rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
|
|
args[j] |= rcbits << (56 - 5);
|
|
hp[0] = 0;
|
|
continue;
|
|
}
|
|
|
|
hp[0] &= ~HPTE_V_VALID; /* leave it locked */
|
|
tlbrb[n] = compute_tlbie_rb(hp[0], hp[1], pte_index);
|
|
indexes[n] = j;
|
|
hptes[n] = hp;
|
|
revs[n] = rev;
|
|
++n;
|
|
}
|
|
|
|
if (!n)
|
|
break;
|
|
|
|
/* Now that we've collected a batch, do the tlbies */
|
|
do_tlbies(kvm, tlbrb, n, global, true);
|
|
|
|
/* Read PTE low words after tlbie to get final R/C values */
|
|
for (k = 0; k < n; ++k) {
|
|
j = indexes[k];
|
|
pte_index = args[j] & ((1ul << 56) - 1);
|
|
hp = hptes[k];
|
|
rev = revs[k];
|
|
remove_revmap_chain(kvm, pte_index, rev, hp[0], hp[1]);
|
|
rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
|
|
args[j] |= rcbits << (56 - 5);
|
|
hp[0] = 0;
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
|
|
unsigned long pte_index, unsigned long avpn,
|
|
unsigned long va)
|
|
{
|
|
struct kvm *kvm = vcpu->kvm;
|
|
unsigned long *hpte;
|
|
struct revmap_entry *rev;
|
|
unsigned long v, r, rb, mask, bits;
|
|
|
|
if (pte_index >= kvm->arch.hpt_npte)
|
|
return H_PARAMETER;
|
|
|
|
hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
|
|
while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
|
|
cpu_relax();
|
|
if ((hpte[0] & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
|
|
((flags & H_AVPN) && (hpte[0] & ~0x7fUL) != avpn)) {
|
|
hpte[0] &= ~HPTE_V_HVLOCK;
|
|
return H_NOT_FOUND;
|
|
}
|
|
|
|
v = hpte[0];
|
|
bits = (flags << 55) & HPTE_R_PP0;
|
|
bits |= (flags << 48) & HPTE_R_KEY_HI;
|
|
bits |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
|
|
|
|
/* Update guest view of 2nd HPTE dword */
|
|
mask = HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
|
|
HPTE_R_KEY_HI | HPTE_R_KEY_LO;
|
|
rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
|
|
if (rev) {
|
|
r = (rev->guest_rpte & ~mask) | bits;
|
|
rev->guest_rpte = r;
|
|
note_hpte_modification(kvm, rev);
|
|
}
|
|
r = (hpte[1] & ~mask) | bits;
|
|
|
|
/* Update HPTE */
|
|
if (v & HPTE_V_VALID) {
|
|
rb = compute_tlbie_rb(v, r, pte_index);
|
|
hpte[0] = v & ~HPTE_V_VALID;
|
|
do_tlbies(kvm, &rb, 1, global_invalidates(kvm, flags), true);
|
|
/*
|
|
* If the host has this page as readonly but the guest
|
|
* wants to make it read/write, reduce the permissions.
|
|
* Checking the host permissions involves finding the
|
|
* memslot and then the Linux PTE for the page.
|
|
*/
|
|
if (hpte_is_writable(r) && kvm->arch.using_mmu_notifiers) {
|
|
unsigned long psize, gfn, hva;
|
|
struct kvm_memory_slot *memslot;
|
|
pgd_t *pgdir = vcpu->arch.pgdir;
|
|
pte_t pte;
|
|
|
|
psize = hpte_page_size(v, r);
|
|
gfn = ((r & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
|
|
memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
|
|
if (memslot) {
|
|
hva = __gfn_to_hva_memslot(memslot, gfn);
|
|
pte = lookup_linux_pte_and_update(pgdir, hva,
|
|
1, &psize);
|
|
if (pte_present(pte) && !pte_write(pte))
|
|
r = hpte_make_readonly(r);
|
|
}
|
|
}
|
|
}
|
|
hpte[1] = r;
|
|
eieio();
|
|
hpte[0] = v & ~HPTE_V_HVLOCK;
|
|
asm volatile("ptesync" : : : "memory");
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
long kvmppc_h_read(struct kvm_vcpu *vcpu, unsigned long flags,
|
|
unsigned long pte_index)
|
|
{
|
|
struct kvm *kvm = vcpu->kvm;
|
|
unsigned long *hpte, v, r;
|
|
int i, n = 1;
|
|
struct revmap_entry *rev = NULL;
|
|
|
|
if (pte_index >= kvm->arch.hpt_npte)
|
|
return H_PARAMETER;
|
|
if (flags & H_READ_4) {
|
|
pte_index &= ~3;
|
|
n = 4;
|
|
}
|
|
rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
|
|
for (i = 0; i < n; ++i, ++pte_index) {
|
|
hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
|
|
v = hpte[0] & ~HPTE_V_HVLOCK;
|
|
r = hpte[1];
|
|
if (v & HPTE_V_ABSENT) {
|
|
v &= ~HPTE_V_ABSENT;
|
|
v |= HPTE_V_VALID;
|
|
}
|
|
if (v & HPTE_V_VALID) {
|
|
r = rev[i].guest_rpte | (r & (HPTE_R_R | HPTE_R_C));
|
|
r &= ~HPTE_GR_RESERVED;
|
|
}
|
|
vcpu->arch.gpr[4 + i * 2] = v;
|
|
vcpu->arch.gpr[5 + i * 2] = r;
|
|
}
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
void kvmppc_invalidate_hpte(struct kvm *kvm, unsigned long *hptep,
|
|
unsigned long pte_index)
|
|
{
|
|
unsigned long rb;
|
|
|
|
hptep[0] &= ~HPTE_V_VALID;
|
|
rb = compute_tlbie_rb(hptep[0], hptep[1], pte_index);
|
|
do_tlbies(kvm, &rb, 1, 1, true);
|
|
}
|
|
EXPORT_SYMBOL_GPL(kvmppc_invalidate_hpte);
|
|
|
|
void kvmppc_clear_ref_hpte(struct kvm *kvm, unsigned long *hptep,
|
|
unsigned long pte_index)
|
|
{
|
|
unsigned long rb;
|
|
unsigned char rbyte;
|
|
|
|
rb = compute_tlbie_rb(hptep[0], hptep[1], pte_index);
|
|
rbyte = (hptep[1] & ~HPTE_R_R) >> 8;
|
|
/* modify only the second-last byte, which contains the ref bit */
|
|
*((char *)hptep + 14) = rbyte;
|
|
do_tlbies(kvm, &rb, 1, 1, false);
|
|
}
|
|
EXPORT_SYMBOL_GPL(kvmppc_clear_ref_hpte);
|
|
|
|
static int slb_base_page_shift[4] = {
|
|
24, /* 16M */
|
|
16, /* 64k */
|
|
34, /* 16G */
|
|
20, /* 1M, unsupported */
|
|
};
|
|
|
|
/* When called from virtmode, this func should be protected by
|
|
* preempt_disable(), otherwise, the holding of HPTE_V_HVLOCK
|
|
* can trigger deadlock issue.
|
|
*/
|
|
long kvmppc_hv_find_lock_hpte(struct kvm *kvm, gva_t eaddr, unsigned long slb_v,
|
|
unsigned long valid)
|
|
{
|
|
unsigned int i;
|
|
unsigned int pshift;
|
|
unsigned long somask;
|
|
unsigned long vsid, hash;
|
|
unsigned long avpn;
|
|
unsigned long *hpte;
|
|
unsigned long mask, val;
|
|
unsigned long v, r;
|
|
|
|
/* Get page shift, work out hash and AVPN etc. */
|
|
mask = SLB_VSID_B | HPTE_V_AVPN | HPTE_V_SECONDARY;
|
|
val = 0;
|
|
pshift = 12;
|
|
if (slb_v & SLB_VSID_L) {
|
|
mask |= HPTE_V_LARGE;
|
|
val |= HPTE_V_LARGE;
|
|
pshift = slb_base_page_shift[(slb_v & SLB_VSID_LP) >> 4];
|
|
}
|
|
if (slb_v & SLB_VSID_B_1T) {
|
|
somask = (1UL << 40) - 1;
|
|
vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT_1T;
|
|
vsid ^= vsid << 25;
|
|
} else {
|
|
somask = (1UL << 28) - 1;
|
|
vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT;
|
|
}
|
|
hash = (vsid ^ ((eaddr & somask) >> pshift)) & kvm->arch.hpt_mask;
|
|
avpn = slb_v & ~(somask >> 16); /* also includes B */
|
|
avpn |= (eaddr & somask) >> 16;
|
|
|
|
if (pshift >= 24)
|
|
avpn &= ~((1UL << (pshift - 16)) - 1);
|
|
else
|
|
avpn &= ~0x7fUL;
|
|
val |= avpn;
|
|
|
|
for (;;) {
|
|
hpte = (unsigned long *)(kvm->arch.hpt_virt + (hash << 7));
|
|
|
|
for (i = 0; i < 16; i += 2) {
|
|
/* Read the PTE racily */
|
|
v = hpte[i] & ~HPTE_V_HVLOCK;
|
|
|
|
/* Check valid/absent, hash, segment size and AVPN */
|
|
if (!(v & valid) || (v & mask) != val)
|
|
continue;
|
|
|
|
/* Lock the PTE and read it under the lock */
|
|
while (!try_lock_hpte(&hpte[i], HPTE_V_HVLOCK))
|
|
cpu_relax();
|
|
v = hpte[i] & ~HPTE_V_HVLOCK;
|
|
r = hpte[i+1];
|
|
|
|
/*
|
|
* Check the HPTE again, including large page size
|
|
* Since we don't currently allow any MPSS (mixed
|
|
* page-size segment) page sizes, it is sufficient
|
|
* to check against the actual page size.
|
|
*/
|
|
if ((v & valid) && (v & mask) == val &&
|
|
hpte_page_size(v, r) == (1ul << pshift))
|
|
/* Return with the HPTE still locked */
|
|
return (hash << 3) + (i >> 1);
|
|
|
|
/* Unlock and move on */
|
|
hpte[i] = v;
|
|
}
|
|
|
|
if (val & HPTE_V_SECONDARY)
|
|
break;
|
|
val |= HPTE_V_SECONDARY;
|
|
hash = hash ^ kvm->arch.hpt_mask;
|
|
}
|
|
return -1;
|
|
}
|
|
EXPORT_SYMBOL(kvmppc_hv_find_lock_hpte);
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|
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|
/*
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* Called in real mode to check whether an HPTE not found fault
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* is due to accessing a paged-out page or an emulated MMIO page,
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* or if a protection fault is due to accessing a page that the
|
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* guest wanted read/write access to but which we made read-only.
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* Returns a possibly modified status (DSISR) value if not
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* (i.e. pass the interrupt to the guest),
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* -1 to pass the fault up to host kernel mode code, -2 to do that
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* and also load the instruction word (for MMIO emulation),
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* or 0 if we should make the guest retry the access.
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|
*/
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long kvmppc_hpte_hv_fault(struct kvm_vcpu *vcpu, unsigned long addr,
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|
unsigned long slb_v, unsigned int status, bool data)
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|
{
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struct kvm *kvm = vcpu->kvm;
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long int index;
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|
unsigned long v, r, gr;
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|
unsigned long *hpte;
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|
unsigned long valid;
|
|
struct revmap_entry *rev;
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|
unsigned long pp, key;
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|
|
|
/* For protection fault, expect to find a valid HPTE */
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valid = HPTE_V_VALID;
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|
if (status & DSISR_NOHPTE)
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|
valid |= HPTE_V_ABSENT;
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|
|
|
index = kvmppc_hv_find_lock_hpte(kvm, addr, slb_v, valid);
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|
if (index < 0) {
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|
if (status & DSISR_NOHPTE)
|
|
return status; /* there really was no HPTE */
|
|
return 0; /* for prot fault, HPTE disappeared */
|
|
}
|
|
hpte = (unsigned long *)(kvm->arch.hpt_virt + (index << 4));
|
|
v = hpte[0] & ~HPTE_V_HVLOCK;
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|
r = hpte[1];
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|
rev = real_vmalloc_addr(&kvm->arch.revmap[index]);
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|
gr = rev->guest_rpte;
|
|
|
|
unlock_hpte(hpte, v);
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|
|
|
/* For not found, if the HPTE is valid by now, retry the instruction */
|
|
if ((status & DSISR_NOHPTE) && (v & HPTE_V_VALID))
|
|
return 0;
|
|
|
|
/* Check access permissions to the page */
|
|
pp = gr & (HPTE_R_PP0 | HPTE_R_PP);
|
|
key = (vcpu->arch.shregs.msr & MSR_PR) ? SLB_VSID_KP : SLB_VSID_KS;
|
|
status &= ~DSISR_NOHPTE; /* DSISR_NOHPTE == SRR1_ISI_NOPT */
|
|
if (!data) {
|
|
if (gr & (HPTE_R_N | HPTE_R_G))
|
|
return status | SRR1_ISI_N_OR_G;
|
|
if (!hpte_read_permission(pp, slb_v & key))
|
|
return status | SRR1_ISI_PROT;
|
|
} else if (status & DSISR_ISSTORE) {
|
|
/* check write permission */
|
|
if (!hpte_write_permission(pp, slb_v & key))
|
|
return status | DSISR_PROTFAULT;
|
|
} else {
|
|
if (!hpte_read_permission(pp, slb_v & key))
|
|
return status | DSISR_PROTFAULT;
|
|
}
|
|
|
|
/* Check storage key, if applicable */
|
|
if (data && (vcpu->arch.shregs.msr & MSR_DR)) {
|
|
unsigned int perm = hpte_get_skey_perm(gr, vcpu->arch.amr);
|
|
if (status & DSISR_ISSTORE)
|
|
perm >>= 1;
|
|
if (perm & 1)
|
|
return status | DSISR_KEYFAULT;
|
|
}
|
|
|
|
/* Save HPTE info for virtual-mode handler */
|
|
vcpu->arch.pgfault_addr = addr;
|
|
vcpu->arch.pgfault_index = index;
|
|
vcpu->arch.pgfault_hpte[0] = v;
|
|
vcpu->arch.pgfault_hpte[1] = r;
|
|
|
|
/* Check the storage key to see if it is possibly emulated MMIO */
|
|
if (data && (vcpu->arch.shregs.msr & MSR_IR) &&
|
|
(r & (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) ==
|
|
(HPTE_R_KEY_HI | HPTE_R_KEY_LO))
|
|
return -2; /* MMIO emulation - load instr word */
|
|
|
|
return -1; /* send fault up to host kernel mode */
|
|
}
|