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a89dfde3dc
This ensures that a NOP is a NOP and not a random other instruction that is also a NOP. It allows simplification of dynamic code patching that wants to verify existing code before writing new instructions (ftrace, jump_label, static_call, etc..). Differentiating on NOPs is not a feature. This pessimises 32bit (DONTCARE) and 32bit on 64bit CPUs (CARELESS). 32bit is not a performance target. Everything x86_64 since AMD K10 (2007) and Intel IvyBridge (2012) is fine with using NOPL (as opposed to prefix NOP). And per FEATURE_NOPL being required for x86_64, all x86_64 CPUs can use NOPL. So stop caring about NOPs, simplify things and get on with life. [ The problem seems to be that some uarchs can only decode NOPL on a single front-end port while others have severe decode penalties for excessive prefixes. All modern uarchs can handle both, except Atom, which has prefix penalties. ] [ Also, much doubt you can actually measure any of this on normal workloads. ] After this, FEATURE_NOPL is unused except for required-features for x86_64. FEATURE_K8 is only used for PTI. [ bp: Kernel build measurements showed ~0.3s slowdown on Sandybridge which is hardly a slowdown. Get rid of X86_FEATURE_K7, while at it. ] Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Alexei Starovoitov <alexei.starovoitov@gmail.com> # bpf Acked-by: Linus Torvalds <torvalds@linuxfoundation.org> Link: https://lkml.kernel.org/r/20210312115749.065275711@infradead.org
111 lines
2.4 KiB
C
111 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/static_call.h>
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#include <linux/memory.h>
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#include <linux/bug.h>
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#include <asm/text-patching.h>
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enum insn_type {
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CALL = 0, /* site call */
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NOP = 1, /* site cond-call */
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JMP = 2, /* tramp / site tail-call */
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RET = 3, /* tramp / site cond-tail-call */
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};
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/*
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* data16 data16 xorq %rax, %rax - a single 5 byte instruction that clears %rax
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* The REX.W cancels the effect of any data16.
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*/
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static const u8 xor5rax[] = { 0x66, 0x66, 0x48, 0x31, 0xc0 };
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static void __ref __static_call_transform(void *insn, enum insn_type type, void *func)
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{
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const void *emulate = NULL;
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int size = CALL_INSN_SIZE;
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const void *code;
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switch (type) {
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case CALL:
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code = text_gen_insn(CALL_INSN_OPCODE, insn, func);
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if (func == &__static_call_return0) {
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emulate = code;
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code = &xor5rax;
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}
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break;
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case NOP:
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code = x86_nops[5];
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break;
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case JMP:
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code = text_gen_insn(JMP32_INSN_OPCODE, insn, func);
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break;
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case RET:
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code = text_gen_insn(RET_INSN_OPCODE, insn, func);
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size = RET_INSN_SIZE;
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break;
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}
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if (memcmp(insn, code, size) == 0)
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return;
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if (unlikely(system_state == SYSTEM_BOOTING))
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return text_poke_early(insn, code, size);
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text_poke_bp(insn, code, size, emulate);
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}
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static void __static_call_validate(void *insn, bool tail)
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{
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u8 opcode = *(u8 *)insn;
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if (tail) {
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if (opcode == JMP32_INSN_OPCODE ||
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opcode == RET_INSN_OPCODE)
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return;
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} else {
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if (opcode == CALL_INSN_OPCODE ||
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!memcmp(insn, x86_nops[5], 5) ||
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!memcmp(insn, xor5rax, 5))
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return;
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}
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/*
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* If we ever trigger this, our text is corrupt, we'll probably not live long.
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*/
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WARN_ONCE(1, "unexpected static_call insn opcode 0x%x at %pS\n", opcode, insn);
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}
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static inline enum insn_type __sc_insn(bool null, bool tail)
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{
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/*
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* Encode the following table without branches:
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*
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* tail null insn
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* -----+-------+------
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* 0 | 0 | CALL
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* 0 | 1 | NOP
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* 1 | 0 | JMP
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* 1 | 1 | RET
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*/
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return 2*tail + null;
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}
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void arch_static_call_transform(void *site, void *tramp, void *func, bool tail)
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{
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mutex_lock(&text_mutex);
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if (tramp) {
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__static_call_validate(tramp, true);
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__static_call_transform(tramp, __sc_insn(!func, true), func);
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}
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if (IS_ENABLED(CONFIG_HAVE_STATIC_CALL_INLINE) && site) {
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__static_call_validate(site, tail);
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__static_call_transform(site, __sc_insn(!func, tail), func);
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}
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mutex_unlock(&text_mutex);
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}
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EXPORT_SYMBOL_GPL(arch_static_call_transform);
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